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v850 family tm 32-/16-bit single-chip microcontroller v851 tm v852 tm v853 tm v854 tm document no. u10243ej4v0um00 (4th edition) date published may 1997 n printed in japan 1995 architecture
notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
v800 series, v810 family, v830 family, v850 family, v805, v810, v820, v821, v830, v851, v852, v853, and v854 are trademarks of nec corporation. unix is a registered trademark licensed by x/open company limited in the us and other countries. windows is a trademark of microsoft corporation. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
nec electronics inc. (u.s.) mountain view, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby sweden tel: 8-63 80 820 fax: 8-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 3
main revisions in this edition page description general v854 is added to target device p. 3 figure of 1.3 product development is modified. p. 7 remark of figure 2-2. program register operations is modified. p. 18 addition of description to 4.1 memory map p. 33 sr is added to 5.3 instruction set operation p. 67 addition of description to remark of saturated add p. 68 addition of description to remark of saturated subtract p. 69 addition of description to remark of saturated subtract immediate p. 70 addition of description to remark of saturated subtract reverse the mark shows major revised points.
preface readers this manual is intended for users who understand the functions of the v850 family in designing systems using the products of the v850 family. purpose this manual presents information on the architecture and instruction set of the v850 family. ? v850 family products ? v851 : m pd703000, 703001, 70p3000 ? v852 : m pd703002, 70p3002 ? v853 note : m pd703003, 70f3003 ? v854 note : m pd703008, 70f3008, 703008y, 70f3008y note under development organization this manual contains the following information: ? register set ? data type ? instruction format and instruction set ? interrupt and exception ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge of electronics engineering, logic circuits, and microcontrollers. to learn about the hardware functions, ? read the users manual C hardware of each device. to learn about the functions of a specific instruction in detail, ? read chapter 5 instruction . to learn about the electrical specifications, ? read the data sheet of each device. to understand the overall functions of the v850 family, ? read this manual in the order of contents. with the v850 family, data consisting of 2 bytes is called a half-word, and data consisting of 4 bytes is called a word.
legend data significance : most significant bits on the left, and least significant bits on the right. active low : (bar over pin or signal name) memory map address : top - high, bottom - low * : footnote caution : important information remark : supplement numeric representation : binary ... or b decimal ... hexadecimal ... h prefixes representing an exponent of 2 (for address space or memory capacity): k (kilo) : 2 10 = 1024 m (mega) : 2 20 = 1024 2 g (giga) : 2 30 = 1024 3 related documents the related documents indicated here may include preliminary version. however, preliminary versions are not marked as such. ? device related documents document name data sheet users manual application table product name hardware architecture register instruction v851 u10987e note 1 u10935e u10243e u10662e u10229e u10988e note 2 v852 u11826e note 3 u10038e u10513e u11827e note 4 v853 to be prepared note 5 u10913e u12036e note 6 v854 to be prepared u10969e notes 1. m pd703000, 703001 2. m pd70p3000 3. m pd703002 4. m pd70p3002 5. m pd703003 6. m pd70f3003
? development tool related documents (users manual) document name document number ie-703002-mc (incircuit emulator) u11595e ie-703003-mc-em1 (v853 peripheral i/o board) u11596e ie-703008-mc-em1 (v854 peripheral i/o board) to be prepared ca850 (c compiler package) operation unix tm based u11013e operation windows tm based u11068e c language u11010e assembly language u10543e rx850 (real-time os) fundamental u11037e technical u11117e nucleus installation u11038e debugger windows based u11158e az850 (system performance analyzer) operation u11181e id850 (c source debugger) operation unix based u12209e operation windows based u11196e installation unix based u12210e
- i - contents chapter 1 introduction ...................................................................................................... ..... 1 1.1 general ..................................................................................................................... .............. 1 1.2 architecture features ....................................................................................................... .... 2 1.3 product development ......................................................................................................... .. 3 1.4 cpu configuration ........................................................................................................... ..... 4 chapter 2 register set ..................................................................................................... ...... 5 2.1 program registers ........................................................................................................... ..... 5 2.1.1 program register set ...................................................................................................... .............. 5 2.2 system registers ............................................................................................................ ...... 8 2.2.1 interrupt status saving registers ......................................................................................... ......... 8 2.2.2 nmi status saving registers ............................................................................................... .......... 9 2.2.3 exception cause register .................................................................................................. ........... 9 2.2.4 program status word ....................................................................................................... ............ 9 2.2.5 system register number .................................................................................................... .......... 11 chapter 3 data type ........................................................................................................ ......... 13 3.1 data format ................................................................................................................. .......... 13 3.1.1 data type and addressing .................................................................................................. ......... 13 3.2 data representation ......................................................................................................... .... 14 3.2.1 integer ................................................................................................................... ...................... 14 3.2.2 unsigned integer .......................................................................................................... ............... 15 3.2.3 bit ....................................................................................................................... ......................... 15 3.3 data alignment .............................................................................................................. ........ 15 chapter 4 address space .................................................................................................... ... 17 4.1 memory map .................................................................................................................. ........ 18 4.2 addressing mode ............................................................................................................. ..... 19 4.2.1 instruction address ....................................................................................................... ............... 19 4.2.2 operand address ........................................................................................................... ............. 22 chapter 5 instruction ....................................................................................................... ....... 25 5.1 instruction format .......................................................................................................... ...... 25 5.2 outline of instructions ..................................................................................................... ..... 28 5.3 instruction set ............................................................................................................. .......... 32 5.4 number of instruction execution clock cycles ................................................................. 90 chapter 6 interrupt and exception .................................................................................. 93 6.1 interrupt servicing ......................................................................................................... ....... 94 6.1.1 maskable interrupt ........................................................................................................ ............... 94 6.1.2 non-maskable interrupt .................................................................................................... ........... 96 6.2 exception processing ........................................................................................................ .. 97 6.2.1 software exception ........................................................................................................ .............. 97 6.2.2 exception trap ............................................................................................................ ................. 98 6.3 restoring from interrupt/exception .................................................................................... 99
- ii - chapter 7 reset ............................................................................................................. .............. 101 7.1 initializing ................................................................................................................ .............. 101 7.2 starting up ................................................................................................................. ........... 101 chapter 8 pipeline .......................................................................................................... ............ 103 8.1 outline of operation ........................................................................................................ ..... 103 8.2 pipeline flow during execution of instructions ................................................................ 104 8.2.1 load instructions ......................................................................................................... ................ 104 8.2.2 store instructions ........................................................................................................ ................ 104 8.2.3 arithmetic operation instructions (excluding multiply and divide instructions) ............................. 104 8.2.4 multiply instructions ..................................................................................................... ................ 105 8.2.5 divide instructions ....................................................................................................... ................ 105 8.2.6 logical operation instructions ............................................................................................ .......... 105 8.2.7 saturation operation instructions ......................................................................................... ........ 106 8.2.8 branch instruction ........................................................................................................ ............... 106 8.2.9 bit manipulation instructions ............................................................................................. .......... 107 8.2.10 special instructions ..................................................................................................... ................ 108 8.3 pipeline disorder ........................................................................................................... ....... 110 8.3.1 alignment hazard .......................................................................................................... .............. 110 8.3.2 referencing execution result of load instruction ......................................................................... 1 11 8.3.3 referencing execution result of multiply instruction .................................................................... 11 1 8.3.4 referencing execution result of ldsr instruction for eipc and fepc ...................................... 112 8.3.5 cautions when creating programs ........................................................................................... ... 112 8.4 additional items related to pipeline ................................................................................... 113 8.4.1 harvard architecture ...................................................................................................... .............. 113 8.4.2 short path ................................................................................................................ .................... 114 appendix a instruction mnemonic (in alphabetical order) ...................................... 115 appendix b instruction list ................................................................................................ ... 123 appendix c instruction op code map ............................................................................... 125 index .......................................................................................................................... .......................... 127
- iii - list of figures figure no. title page 1-1 internal configuration ...................................................................................................... ...... 4 2-1 program registers ........................................................................................................... ..... 6 2-2 program register operations ............................................................................................... 7 2-3 system registers ............................................................................................................ ...... 8 4-1 memory map .................................................................................................................. ....... 18 4-2 relative addressing (jr disp22/jarl disp22, reg2) ............................................................ 19 4-3 relative addressing (bcond disp9) ....................................................................................... 20 4-4 register addressing (jmp [reg1]) ......................................................................................... 21 4-5 based addressing ............................................................................................................ ..... 22 4-6 based addressing ............................................................................................................ ..... 23 4-7 bit addressing .............................................................................................................. ......... 24 6-1 maskable interrupt servicing format .................................................................................... 95 6-2 non-maskable interrupt servicing format ............................................................................ 96 6-3 software exception processing format ................................................................................ 97 6-4 illegal instruction code .................................................................................................... ...... 98 6-5 exception trap processing format ....................................................................................... 98 6-6 restoration from interrupt/exception .................................................................................... 99 8-1 example of executing nine standard instructions ................................................................ 103 8-2 access times (in clocks) .................................................................................................... ... 104 8-3 align hazard example ........................................................................................................ ... 110 8-4 example of execution result of load instruction .................................................................. 111 8-5 example of execution result of multiply instruction ............................................................. 111
- iv - list of tables table no. title page 2-1 system register number ...................................................................................................... 11 5-1 load/store instructions ..................................................................................................... .... 28 5-2 arithmetic operation instructions .......................................................................................... 2 8 5-3 saturated operation instructions .......................................................................................... 29 5-4 logical operation instructions .............................................................................................. .29 5-5 branch instructions ......................................................................................................... ...... 30 5-6 bit manipulation instructions ............................................................................................... .. 31 5-7 special instructions ........................................................................................................ ....... 31 5-8 conditional branch instructions ............................................................................................ 4 1 5-9 condition codes ............................................................................................................. ....... 72 5-10 list of number of instruction execution clock cycles ........................................................... 90 6-1 interrupt/exception codes ................................................................................................... .. 94 7-1 register status after reset ................................................................................................. .. 101 a-1 instruction mnemonic (in alphabetical order) ........................................................................ 116 b-1 mnemonic list ............................................................................................................... ........ 123 b-2 instruction set ............................................................................................................. .......... 124
chapter 1 introduction the v850 family is a collection of necs single-chip microcontrollers that have a cpu core using the risc microprocessor technology of the v800 series tm , with on-chip rom/ram and peripheral i/os, etc. the v850 family of microcontrollers provides a migration path to the existing necs original single-chip microcontroller 78k series, and boasts higher cost-performance. this chapter briefly outlines the v850 family. 1.1 general real-time control systems are used in a wide range of applications, including: ? office equipment such as hdds (hard disk drives), ppcs (plain paper copiers), printers, and facsimiles, ? automobile electronics such as engine control systems and abss (antilock braking systems), and ? factory automation equipment such as nc (numerical control) machine tools and various controllers. the great majority of these systems employed 8-bit or 16-bit microcontrollers so far. however,the perform- ance level of these microcontrollers has become inadequate in recent years as control operations have risen in complexity, leading to the development of increasingly complicated instruction sets and hardware design. as a result, the need has arisen for a new generation of microcontrollers operable at much higher frequencies to achieve an acceptable level of performance under today's more demanding requirements. the v850 family of microcontrollers was developed to satisfy this need. this family uses risc architecture that can provide maximum performance with simpler hardware, allowing users to obtain a performance ap- proximately 15 times higher than that of the existing 78k/iii series and 78k/iv series cisc single-chip microcontrollers at a lower total cost. in addition to the basic instructions of conventional risc cpus, the v850 family is provided with special instructions such as saturate, bit manipulate, and multiply/divide (executed by a hardware multiplier) instruc- tions, which are especially suited for digital servo control systems. moreover, instruction formats are de- signed for maximum compiler coding efficiency, allowing the reduction of object code sizes. 1
chapter 1 introduction 2 1.2 architecture features ? high-performance 32-bit architecture for embedded control ? number of instructions : 74 ? 32-bit general registers : 32 ? load/store instructions in long/short format ? 3-operand instruction ? 5-stage pipeline of 1 clock cycle per stage ? hardware interlock on register/flag hazards ? memory space program space : 16 mb linear data space : 4 gb linear ? special instructions ? saturation operation instructions ? bit manipulation instructions ? on-chip multiplier executing multiplication in 1 to 2 clocks (16 bits 16 bits ? 32 bits)
3 chapter 1 introduction 1.3 product development the v850 family is part of the v800 series and consists of single-chip microcontrollers using a risc microprocessor core. while the v810 family tm of microprocessors is intended for data processing, the v850 family is targeted for embedded control systems, and can be used in a wide variety of applications. product development v800 series v810 family v810 tm v805 tm v820 tm v821 tm v830 tm v830 family tm v83x v850family v850/xxx v854 v852 v853 v851
chapter 1 introduction 4 1.4 cpu configuration figure 1-1 shows the internal configuration of the v850 family. figure 1-1. internal configuration the function of each hardware block is as follows: cpu executes almost all instructions such as address calculation, arithmetic and logical operation, and data transfer in one clock by using a 5-stage pipeline. contains dedicated hardware such as a multiplier (16 16 bits) and a barrel shifter (32 bits/clock) to execute complicated instructions at high speeds. internal rom rom or eprom mapped from address 00000000h. can be accessed by the cpu in one clock during instruction fetch. internal ram ram mapped to a space preceding address ffffefffh. can be accessed by the cpu in one clock during data access. internal peripheral i/o peripheral i/o area mapped from address fffff000h. bcu starts a necessary bus cycle based on a physical address obtained by the cpu. if the cpu does not issue a request for starting a bus cycle, the bcu generates a prefetch address, and prefetches an instruction code. the prefetched instruction code is loaded to an internal instruction queue. bcu cpu internal rom pc multiplier 16 16 ? 32 32-bit barrel shifter internal ram rom/ prom system register general register 32 bits 32 prefetch control bus control instruction queue internal bus alu internal peripheral i/o
chapter 2 register set the registers of the v850 family can be classified into two types: program register sets that can be used for general programming, and system registers that can control the execution environment. all the registers are 32 bits wide. 2.1 program registers 2.1.1 program register set (1) general registers the v850 family has thirty-two general registers, r0 through r31. all these registers can be used for data or address storage. however, r0 and r30 are implicitly used by instructions, and care must be exercised in using these registers. r0 is a register that always holds 0, and is used for operations and offset 0 addressing. r30 is used as a base pointer when accessing memory using the sld and sst instructions. r1, r2, r3, r4, r5, and r31 are implicitly used by the assembler and c compiler. before using these registers, therefore, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. 5
chapter 2 register set 6 figure 2-1. program registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 zero register reserved for address generation interrupt stack pointer stack pointer (sp) global pointer (gp) text pointer (tp) element pointer (ep) link pointer (lp) pc program counter 31 0
7 chapter 2 register set figure 2-2. program register operations name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as working register for address generation. r2 interrupt stack pointer used as stack pointer for interrupt handler. r3 stack pointer used for stack frame generation when function is called. r4 global pointer used to access global variable in data area. r5 text pointer used as register for pointing start address of text area note . r6 through address/data variable registers r29 r30 element pointer used as base pointer for address generation when memory is accessed. r31 link pointer used when compiler calls function. pc program counter holds instruction address during program execu- tion. note text area : area where program code is placed. remark for detailed descriptions of r1 to r31 used by assembler and c compiler, see the c compiler package (ca850) users manual . (2) program counter this register holds an instruction address during program execution. the lower 24 bits of this register are valid, and bits 31 through 24 are reserved fields (fixed to 0). if a carry occurs from bit 23 to 24, it is ignored. bit 0 is always fixed to 0, and execution cannot branch to an odd address. remark rfu : reserved field (reserved for future use) 31 pc rfu 0 24 23 1 0
chapter 2 register set 8 2.2 system registers the system registers control the status of the v850 family and holds information on interrupts. figure 2-3. system registers 2.2.1 interrupt status saving registers two interrupt status saving registers are provided: eipc and eipsw. the contents of the pc and psw are respectively saved in these registers if an exception or interrupt occurs. if the nmi occurs, however, the contents of the pc and psw are saved to nmi status saving registers. when an exception or interrupt occurs, the address of the following instruction is saved in the eipc register. if an interrupt occurs while a division (divh) instruction is executed, the address of the division instruction currently being executed is saved. the current value of the psw is saved to the eipsw. because only one pair of interrupt status saving registers is provided, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 24 through 31 of the eipc and bits 8 through 31 of the eipsw are fixed to 0. eipc eipsw exception/interrupt pc exception/interrupt psw 31 0 fepc fepsw fatal error pc fatal error psw ecr exception cause register psw program status word 31 eipc pc 0 31 eipsw psw 0
9 chapter 2 register set 2.2.2 nmi status saving registers the v850 family is provided with two nmi status saving registers: fepc and fepsw. the contents of the pc and psw are respectively saved in these registers when an nmi occurs. the value saved to the fepc is, like the eipc, the address of the instruction next to the one executed when the nmi has occurred (if the nmi occurs while a division (divh) instruction is executed, the address of the division instruction under execution is saved). the current value of the psw is saved to the fepsw. bits 24 through 31 of the fepc and bits 8 through 31 of the fepsw are fixed to 0. 2.2.3 exception cause register the exception cause register (ecr) holds the cause information of an exception, maskable interrupt, or nmi when any of these events occur. the ecr holds a code which identifies each interrupt source. this is a read-only register, and therefore, no data can be written to it by using the ldsr instruction. bit position field function 31 - 16 fecc fatal error cause code nmi code 15 - 0 eicc exception/interrupt cause code exception/interrupt code 2.2.4 program status word the program status word is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the cpu. if the contents of the psw register are modified by the ldsr instruction, the psw will assume the new value immediately after the ldsr instruction has been executed. in setting the id flag to 1, however, interrupts are already disabled even while the ldsr instruction is executing. 31 ecr fecc 0 eicc 16 15 31 psw rfu 0 1 2 3 4 5 6 7 n p s o v c y s a t i d e p z 8 31 fepc pc 0 31 fepsw psw 0
chapter 2 register set 10 bit position flag function 31 - 8 rfu reserved for future use reserved field (fixed to 0). 7 np nmi pending indicates that nmi processing is in progress. this flag is set when nmi is granted. the nmi request is then masked, and multiple interrupts are disabled. np = 0: nmi processing is not in progress np = 1: nmi processing is in progress 6 ep exception pending indicates that exception processing is in progress. this flag is set when an excep- tion occurs. ep = 0: exception processing is not in progress ep = 1: exception processing is in progress 5 id interrupt disable indicates whether external interrupt request can be accepted. id = 0: interrupt can be accepted id = 1: interrupt cannot be accepted 4 sat note saturated math result indicates that an overflow has occurred in a saturate operation and the result is saturated. this is a cumulative flag. once the result is saturated, the flag is set to 1 and is not reset to 0 even if the next result does not saturate. to reset this flag, load data to psw. this flag is neither set nor reset by general arithmetic operation instruction. sat = 0: not saturated sat = 1: saturated 3 cy carry indicates whether carry or borrow occurred as a result of the operation. cy = 0: carry or borrow did not occur cy = 1: carry or borrow occurred 2ov note overflow indicates whether overflow occurred as a result of the operation. ov = 0: overflow did not occur ov = 1: overflow occurred 1s note sign indicates whether the result of the operation is negative s = 0: result is positive or zero s = 1: result is negative 0 z zero indicates whether the result of the operation is zero z = 0: result is not zero z = 1: result is zero note in the case of saturate instructions, the sat, s, and ov flags will be set accordingly by the result of the operation as shown in the table below. note that the sat flag is set to 1 only when the ov flag has been set due to an overflow condition caused by a saturate instruction. status of operation result sat-s-ov result of saturation processing maximum positive value is 1 0 1 7fffffffh exceeded maximum negative value 1 1 1 80000000h is exceeded others 0 0 operation result
11 chapter 2 register set 2.2.5 system register number data in the system registers is accessed by using the load/store system register instructions, ldsr and stsr. each register is assigned a unique number which is referenced by the ldsr and stsr instructions. table 2-1. system register number number system register operand specification ldsr stsr 0 eipc ?? 1 eipsw ?? 2 fepc ?? 3 fepsw ?? 4 ecr ? 5 psw ?? 6 - 31 reserved : accessing prohibited ? : accessing enabled reserved : accessing registers in this range is prohibited and will lead to undefined results. caution when using the ldsr instruction with the eipc and fepc registers, only even address values should be specified. after interrupt servicing has ended with a reti instruction, bit 0 in the eipc and fepc registers will be ignored and assumed to be zero when the pc is restored.
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chapter 3 data type 3.1 data format the v850 family supports the following data types: ? integer (8, 16, 32 bits) ? unsigned integer (8, 16, 32 bits) ? bit 3.1.1 data type and addressing the v850 family supports three types of data lengths: word (32 bits), half-word (16 bits), and byte (8 bits). byte 0 of any data is always the least significant byte (this is called little endian) and shown at the rightmost position in figures throughout this manual. the following paragraphs describe the data format where data of fixed length is in memory. (1) byte (byte) a byte is 8-bit contiguous data that starts from any byte boundary note . each bit is assigned a number from 0 to 7. the lsb (least significant bit) is bit 0 and the msb (most significant bit) is bit 7. a byte is specified by its address a. (2) half-word (half-word) a half-word is 2-byte (16-bit) contiguous data that starts from any half-word boundary note . each bit is assigned a number from 0 to 15. the lsb is bit 0 and the msb is bit 15. a half-word is specified by its address a (with the lowest bit fixed to 0), and occupies 2 bytes a and a+1. data 0 7 address a data 0 7 address a 8 15 a+1 13
chapter 3 data type 14 (3) word (word) a word is 4-byte (32-bit) contiguous data that starts from any word boundary note . each bit is assigned a number from 0 to 31. the lsb is bit 0 and the msb is bit 31. a word is specified by its address a (with the 2 lowest bits fixed to 0), and occupies 4 bytes a, a+1, a+2, and a+3. (4) bit (bit) a bit is 1-bit data at the nth bit position in 8-bit data that starts from any byte boundary note . a bit is specified by its address a and bit number n. note refer to 3.3 data alignment . 3.2 data representation 3.2.1 integer with the v850 family, an integer is expressed as a binary number of 2s complement and is 8, 16, or 32 bits long. regardless of its length, the bit 0 of an integer is the least significant bit. the higher the bit number, the more significan t the bit. because 2s complement is used, the most significant bit is used as a sign bit. data length range byte 8 bits C128 to +127 half-word 16 bits C32768 to +32767 word 32 bits C2147483648 to +2147483647 data 0 7 address a 8 15 a+1 a+2 a+3 16 23 24 31 data 0 n address a 7 bit number byte of address a
15 chapter 3 data type 3.2.2 unsigned integer while an integer is data that can take either a positive or a negative value, an unsigned integer is an integer that is not negative. like an integer, an unsigned integer is also expressed as 2s complement and is 8, 16, or 32 bits long. regardless of its length, the bit 0 of an unsigned integer is the least significant bit, and the higher the bit number, the more significant the bit. however, no sign bit is used. data length range byte 8 bits 0 to 255 half-word 16 bits 0 to 65535 word 32 bits 0 to 4294967295 3.2.3 bit the v850 family can handle 1-bit data that can take a value of 0 (cleared) or 1 (set). bit manipulation can be performed only to 1-byte data in the memory space in the following four ways: ? set ? clear ? invert ? test 3.3 data alignment with the v850 family, word data to be allocated in memory must be aligned at an appropriate boundary. therefore, word data must be aligned at a word boundary (the lower 2 bits of the address are 0), and half-word data must be aligned at a half-word boundary (the lowest bit of the address is 0). if data is not aligned at a boundary, the data is accessed with the lowest bit(s) of the address (lower 2 bits in the case of word data and lowest 1 bit in the case of half-word data) automatically masked. this will cause lost of data and truncation of the least significant bytes. byte data can be placed at any address.
[memo] 16
chapter 4 address space the v850 family supports a 4-gb linear address space. both memory and i/o are mapped to this address space ( memory-mapped i/o ). the v850 family outputs 32-bit addresses to the memory and i/o. the maximum address is 2 32 C1. byte ordering is little endian. byte data allocated at each address is defined with bit 0 as lsb and bit 7 as msb. in regards to multiple-byte data, the byte with the lowest address value is defined to have the lsb and the byte with the highest address value is defined to have the msb. data consisting of 2 bytes is called a half-word, and 4-byte data is called a word. in this users manual, data consisting of 2 or more bytes is illustrated as below, with the lower address shown on the right and the higher address on the left. data 0 7 address a 8 15 a+1 data 0 7 address a 8 15 a+1 data 0 7 address a 16 23 a+2 24 31 a+3 byte of address a half-word at address a word at address a 17
chapter 4 address space 18 4.1 memory map the v850 family employs a 32-bit architecture and supports a linear address space (data space) of up to 4 gb. it supports a linear address space (program space) of up to 16 mb for instruction addressing. figure 4-1 shows the memory map of the v850 family. the capacity of the on-chip rom and ram depends on each product. for details, refer to the memory map section in the user's manual-hardware of each product. figure 4-1. memory map ffffffffh ffffefffh 00000000h peripheral i/o 4 gb linear internal ram internal rom/prom
19 chapter 4 address space 4.2 addressing mode the cpu generates two types of addresses: instruction addresses used for instruction fetch and branch operations; and operand addresses used for data access. 4.2.1 instruction address an instruction address is determined by the contents of the program counter (pc), and is automatically incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction has been executed. when a branch instruction is executed, the branch destination address is loaded into the pc using one of the following two addressing modes: (1) relative address (pc relative) the signed 9- or 22-bit data of an instruction code (displacement: disp) is added to the value of the program counter (pc). at this time, the displacement is treated as 2s complement data with bits 8 and 21 serving as sign bits. this addressing is used for bcond disp9, jr disp22, and jarl disp22, reg2 instructions. figure 4-2. relative addressing (jr disp22/jarl disp22, reg2) 31 24 23 00000000 pc 0 0 31 22 21 sign extension s disp22 0 0 31 24 23 00000000 pc 0 0 memory to be manipulated
chapter 4 address space 20 figure 4-3. relative addressing (bcond disp9) 31 24 23 00000000 pc 0 0 31 9 8 sign extension s disp9 0 0 31 24 23 00000000 pc 0 0 memory to be manipulated
21 chapter 4 address space (2) register addressing (address indirect) the contents of a general register (r0 - r31) specified by an instruction are transferred to the program counter (pc). this addressing is applied to the jmp [reg1] instruction. figure 4-4. register addressing (jmp [reg1]) 31 0 31 24 23 00000000 pc 0 0 memory to be manipulated rn
chapter 4 address space 22 4.2.2 operand address when an instruction is executed, the register or memory area to be accessed is specified in one of the following four addressing modes: (1) register addressing the general register (may be system register) specified in the general register specification field is accessed as operand. this addressing mode applies to instructions using the operand format reg1, reg2, or regid. (2) immediate addressing the 5-bit or 16-bit data for manipulation is contained directly in the instruction. this addressing mode applies to instructions using the operand format imm5, imm16, vector, or cccc. remark vector : operand that is 5-bit immediate data to specify trap vector (00h-1fh), and is used in trap instruction. cccc : operand consisting of 4-bit data used in setf instruction to specify condition code. assigned as part of instruction code as 5-bit immediate data by appending 1-bit 0 above highest bit. (3) based addressing the following two types of based addressing are supported: (a) type 1 the address of the data memory location to be accessed is determined by adding the value in the specified general register to the 16-bit displacement value contained in the instruction. this addressing mode applies to instructions using the operand format disp16 [reg1]. figure 4-5. based addressing 31 reg1 0 memory to be manipulated 31 16 15 disp16 0 sign extension
23 chapter 4 address space (b) type 2 the address of the data memory location to be accessed is determined by adding the value in the 32-bit element pointer (r30) to the 7- or 8-bit displacement value contained in the instruction. this addressing mode applies to sld and sst instructions. figure 4-6. based addressing 31 r30 (element pointer) 0 memory to be manipulated 31 7 disp8 or disp7 0 (zero extension) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte access = disp7 half-word access and word access = disp8
chapter 4 address space 24 (4) bit addressing this addressing is used to access 1 bit (specified with bit#3 of 3-bit data) among 1 byte of the memory space to be manipulated by using an operand address which is the sum of the contents of a general register and a 16- bit displacement sign-extended to a word length. this addressing mode applies only to bit manipulate instructions. figure 4-7. bit addressing remark n : bit position specified with 3-bit data (bit#3) (n = 0 - 7) memory to be manipulated 31 reg1 0 31 16 15 disp16 0 sign extension n
chapter 5 instruction 5.1 instruction format the v850 family has two types of instruction formats: 16-bit and 32-bit. the 16-bit instructions include binary operation, control, and conditional branch instructions, and the 32-bit instructions include load/store, jump, and instructions that handle 16-bit immediate data. some instructions have an unused field (rfu). this field is reserved for future expansion and must be fixed to 0. an instruction is actually stored in memory as follows: ? lower bytes of instruction (including bit 0) ? lower address ? higher bytes of instruction (including bit 15 or 31) ? higher address (1) reg-reg instruction (format i) a 16-bit instruction format having a 6-bit op code field and two general register specification fields for operand specification. (2) imm-reg instruction (format ii) a 16-bit instruction format having a 6-bit op code field, 5-bit immediate field, and a general register specification field. (3) conditional branch instruction (format iii) a 16-bit instruction format having a 4-bit op code field, 4-bit condition code, and an 8-bit displacement. 15 11 10 5 4 0 reg2 opcode reg1 15 11 10 5 4 0 reg2 opcode imm 15 11 10 6 4 0 disp opcode cond disp 3 7 25
chapter 5 instruction 26 (4) 16-bit load/store instruction (format iv) a 16-bit instruction format having a 4-bit op code field, a general register specification field, and a 7-bit displacement (or 6-bit displacement + 1-bit sub-op code). (6) 3-operand instruction (format vi) a 32-bit instruction format having a 6-bit op code field, two general register specification fields, and a 16-bit immediate field. (7) 32-bit load/store instruction (format vii) a 32-bit instruction format having a 6-bit op code field, two general register specification fields, and a 16-bit displacement (or 15-bit displacement + 1-bit sub-op code). (5) jump instruction (format v) a 32-bit instruction format having a 5-bit op code field, a general register specification field, and a 22-bit displacement. 15 11 10 5 60 reg2 opcode disp disp/sub-opcode 1 7 15 11 10 16 opcode disp 0 031 reg2 17 65 15 11 10 16 opcode imm 0 031 reg2 4 5 reg1 15 11 10 16 opcode disp 031 reg2 4 5 reg1 disp/sub-opcode 17
27 chapter 5 instruction (8) bit manipulation instruction (format viii) a 32-bit instruction format having a 6-bit op code field, 2-bit sub-op code, 3-bit bit specification field, a general register field, and a 16-bit displacement. (9) extended instruction format 1 (format ix) a 32-bit instruction format having a 6-bit op code field, 6-bit sub-op code, and two general register specification fields (one field may be regid or cond). (10) extended instruction format 2 (format x) a 32-bit instruction format having a 6-bit op code field and 6-bit sub op code. remark rfu : reserved field (reserved for future use) 15 11 10 16 opcode disp 031 bit # 4 5 reg1 sub 14 13 15 11 10 16 opcode sub-opcode 031 reg2 4 5 reg1/regid/cond rfu rfu 27 26 20 21 15 11 10 16 opcode sub-opcode 031 rfu 4 5 rfu rfu 27 26 20 21 13 12 rfu/sub-opcode rfu/immediate/vector
chapter 5 instruction 28 5.2 outline of instructions load/store instructions ...................... transfer data from memory to a register or from a register to memory. table 5-1. load/store instructions sld ld sst st arithmetic operation instructions ..... add, subtract, multiply, divide, transfer, or compare data between regis- ters. table 5-2. arithmetic operation instructions mov movhi movea add addi sub subr mulh mulhi divh cmp setf
29 chapter 5 instruction saturated operation instructions ...... execute saturation addition or subtraction. if the result of the operation exceeds the maximum positive value (7fffffffh), 7fffffffh is returned. if the result exceeds the negative value (80000000h), 80000000h is returned. table 5-3. saturated operation instructions satadd satsub satsubi satsubr logical operation instructions .......... these instructions include logical operation instructions and shift instruc- tions. the shift instructions include arithmetic shift and logical shift instructions. operands can be shifted by two or more bit positions in one clock cycle by the universal barrel shifter. table 5-4. logical operation instructions tst or ori and andi xor xori not shl shr sar
chapter 5 instruction 30 branch instructions ...................... branch operations include unconditional branch along with conditional branch instructions which alter the flow of control, depending on the status of conditional flags in the psw. program control can be transferred to the address specified by a branch instruction. table 5-5. branch instructions jmp jr jarl bgt bge blt ble bh bnl bl bnh be bne bv bnv bn bp bc bnc bz bnz br bsa
31 chapter 5 instruction bit manipulation instructions ...... execute a logical operation to bit data in memory. only a specified bit is affected as a result of executing a bit manipulation instruction. table 5-6. bit manipulation instructions set1 clr1 not1 tst1 special instructions ...................... these instructions are special in that they do not fall in any of the categories of instructions described above. table 5-7. special instructions ldsr stsr trap reti halt di ei nop
chapter 5 instruction 32 symbol reg1 reg2 bit#3 imm disp regid vector cccc ep meaning general register (used as source register) general register (mainly used as destination register. some are also used as source registers) 3-bit data for specification bit number -bit immediate -bit displacement system register number 5-bit data for trap vector (00h-1fh) specification 4-bit data for condition code specification element pointer (r30) mnemonic of instruction meaning of instruction instruction format indicates the description and operand of the instruction. the following symbols are used in description of an operand: 5.3 instruction set example of instruction description
33 chapter 5 instruction meaning assignment general register system register zero-extends n to word sign-extends n to word reads data of size b from address a writes data b of size c to address a reads bit b from address a writes c to bit b of address a performs saturation processing of n. if n 3 7fffffffh as result of calculation, 7fffffffh. if n 80000000h as result of calculation, 80000000h. reflects result on flag byte (8 bits) half-word (16 bits) word (32 bits) add subtract bit concatenation multiply divide and or exclusive or logical negate logical left shift logical right shift arithmetic right shift symbol ? gr [ ] sr [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) result byte halfword word + C || ? and or xor not logically shift left by logically shift right by arithmetically shift right by operation describes the function of the instruction. the following symbols are used: format indicates instruction format number.
chapter 5 instruction 34 op code describes the separate bit fields of the instruction opcode. the following symbols are used: symbol r r d i cccc bbb meaning 1-bit data of code specifying reg1 or regid 1-bit data of code specifying reg2 1-bit data of displacement 1-bit data of immediate 4-bit data for condition code specification 3-bit data for bit number specification flag indicates the flags which are altered after executing the instruction. cy C ? indicates that the flag is not affected. ov 0 ? indicates that the flag is cleared to 0. s1 ? indicates that the flag is set to 1. zC sat C instruction describes the function of the instruction. explanation explains the operation of the instruction. remark supplementary information on the instruction caution important cautions regarding use of this instruction
35 chapter 5 instruction mnemonic sld.b sld.h sld.w ld.b ld.h ld.w sst.b sst.h sst.w st.b st.h st.w mov movhi movea add addi sub subr mulh mulhi divh cmp setf satadd satsub satsubi satsubr function load/store instructions load byte load half-word load word load byte load half-word load word store byte store half-word store word store byte store half-word store word arithmetic instructions move move high half-word move effective address add add immediate subtract subtract reverse multiply half-word multiply half-word immediate divide half-word compare set flag condition saturate instructions saturated add saturated subtract saturated subtract immediate saturated subtract reverse instruction list mnemonic tst or ori and andi xor xori not shl shr sar jmp jr jarl bcond set1 clr1 not1 tst1 ldsr stsr trap reti halt di ei nop function logical operation instructions test or or immediate and and immediate exclusive-or exclusive-or immediate not shift logical left shift logical right shift arithmetic right branch instructions jump jump relative jump and register link branch on condition code bit manipulation instructions set bit clear bit not bit test bit special instructions load system register store system register trap return from trap or interrupt halt disable interrupt enable interrupt no operation
chapter 5 instruction 36 add add instruction format (1) add reg1, reg2 (2) add imm5, reg2 operation (1) gr [reg2] ? gr [reg2] + gr [reg1] (2) gr [reg2] ? gr [reg2] + sign-extend (imm5) format (1) format i (2) format ii op code 15 0 (1) rrrrr001110rrrrr 15 0 (2) rrrrr010010iiiii flag cy 1 if a carry occurs from msb; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise 0. sat C instruction (1) add add register (2) add add immediate (5-bit) explanation (1) adds the word data of general register reg1 to the word data of general register reg2, and stores the result to general register reg2. the data of general register reg1 is not affected. (2) adds 5-bit immediate data, sign-extended to word length, to the word data of general register reg2, and stores the result to general register reg2.
37 chapter 5 instruction addi add immediate instruction format addi imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] + sign-extend (imm16) format format vi op code 15 0 31 16 rrrrr110000rrrrr iiiiiiiiiiiiiiii flag cy 1 if a carry occurs from msb; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise 0. sat C instruction addi add immediate explanation adds 16-bit immediate data, sign-extended to word length, to the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected.
chapter 5 instruction 38 and and instruction format and reg1, reg2 operation gr [reg2] ? gr [reg2] and gr [reg1] format format i op code 15 0 rrrrr001010rrrrr flag cy C ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise 0. sat C instruction and and explanation ands the word data of general register reg2 with the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected.
39 chapter 5 instruction andi and immediate instruction format andi imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] and zero-extend (imm16) format format vi op code 15 0 31 16 rrrrr110110rrrrr iiiiiiiiiiiiiiii flag cy C ov 0 s0 z 1 if the result of an operation is 0; otherwise 0. sat C instruction andi and immediate (16-bit) explanation ands the word data of general register reg1 with the value of the 16-bit immediate data, zero- extended to word length, and stores the result to general register reg2. the data of general register reg1 is not affected.
chapter 5 instruction 40 bcond branch on condition code instruction format bcond disp9 operation if conditions are satisfied then pc ? pc + sign-extend (disp9) format format iii op code 15 0 ddddd1011dddcccc dddddddd is the higher 8 bits of disp9. flag cy C ov C sC zC sat C instruction bcond branch on condition code with 9-bit displacement explanation tests a condition flag specified by the instruction. branches if a specified condition is satisfied; otherwise, executes the next instruction. the branch destination pc holds the sum of the current pc value and 9-bit displacement, which is 8-bit immediate shifted 1 bit and sign- extended to word length. remark bit 0 of the 9-bit displacement is masked to 0. the current pc value used for calculation is the address of the first byte of this instruction. if the displacement value is 0, therefore, the branch destination is this instruction itself.
41 chapter 5 instruction table 5-8. conditional branch instructions instruction condition code status of condition flag branch condition (cccc) signed bgt 1111 ( (s xor ov) or z) = 0 greater than signed integer bge 1110 (s xor ov) = 0 greater than or equal signed blt 0110 (s xor ov) = 1 less than signed ble 0111 ( (s xor ov) or z) = 1 less than or equal signed unsigned bh 1011 (cy or z) = 0 higher (greater than) integer bnl 1001 cy = 0 not lower (greater than or equal) bl 0001 cy = 1 lower (less than) bnh 0011 (cy or z) = 1 not higher (less than or equal) common be 0010 z = 1 equal bne 1010 z = 0 not equal others bv 0000 ov = 1 overflow bnv 1000 ov = 0 no overflow bn 0100 s = 1 negative bp 1100 s = 0 positive bc 0001 cy = 1 carry bnc 1001 cy = 0 no carry bz 0010 z = 1 zero bnz 1010 z = 0 not zero br 0101 C always (unconditional) bsa 1101 sat = 1 saturated caution if executing a conditional branch instruction of a signed integer (bgt, bge, blt, or ble) when the sat flag is set to 1 as a result of executing a saturated operation instruction, the branch condition loses its meaning. in ordinary arithmetic operations, if an overflow condition occurs, the s flag is inverted (0 ? 1 or 1 ? 0). this is because the result is a negative value if it exceeds the maximum positive value and it is a positive value if it exceeds the maximum negative value. however, when a saturated operation instruction is executed, and if the result exceeds the maximum positive value, the result is saturated with a positive value; if the result exceeds the maximum negative value, the result is saturated with a negative value. unlike the ordinary operation, therefore, the s flag is not inverted even if an overflow occurs. hence, the s flag of the psw is affected differently when the instruction is a saturate operation, as opposed to an ordinary arithmetic operation. a branch condition which is an xor of s and ov flags will therefore, have no meaning.
chapter 5 instruction 42 clr1 clear bit instruction format clr1 bit#3, disp16 [reg1] operation adr ? gr [reg1] + sign-extend (disp16) z flag ? not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) format format viii op code 15 0 31 16 10bbb111110rrrrr dddddddddddddddd flag cy C ov C sC z 1 if bit no.bit#3 of memory disp16 [reg1] = 0. 0 if bit no.bit#3 of memory disp16 [reg1] = 1. sat C instruction clr1 clear bit explanation adds the data of general register reg1 to the 16-bit displacement, sign-extended to word length, to generate a 32-bit address. then clears the bit, specified by the bit number of 3 bits, of the byte data referenced by the generated address. not specified bit is not affected. remark the z flag of the psw indicates whether the specified bit was a 0 or 1 before this instruction is executed. it does not indicate the content of the specified bit after this instruction has been executed.
43 chapter 5 instruction cmp compare instruction format (1) cmp reg1, reg2 (2) cmp imm5, reg2 operation (1) result ? gr [reg2] C gr [reg1] (2) result ? gr [reg2] C sign-extend (imm5) format (1) format i (2) format ii op code 15 0 (1) rrrrr001111rrrrr 15 0 (2) rrrrr010011iiiii flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 overflow occurs; otherwise 0. s 1 if the result of the operation is negative; otherwise, 0. z 1 if the result of the operation is 0; otherwise, 0. sat C instruction (1) cmp compare register (2) cmp compare immediate (5-bit) explanation (1) compares the word data of general register reg2 with the word data of general register reg1, and indicates the result by using the condition flags. to compare, the contents of general register reg1 are subtracted from the word data of general register reg2. the data of general registers reg1 and reg2 are not affected. (2) compares the word data of general register reg2 with 5-bit immediate data, sign-extended to word length, and indicates the result by using the condition flags. to compare, the contents of the sign-extended immediate data is subtracted from the word data of general register reg2. the data of general register reg2 is not affected.
chapter 5 instruction 44 di disable interrupt instruction format di operation psw.id ? 1 (disables maskable interrupt) format format x op code 15 0 31 16 0000011111100000 0000000101100000 flag cy C ov C sC zC sat C id 1 instruction di disable interrupt explanation sets the id flag of the psw to 1 to disable the acknowledgement of maskable interrupts during executing this instruction. remark interrupts are not sampled during execution of this instruction. the id flag actually becomes valid at the start of the next instruction. but because interrupts are not sampled during instruction execution, interrupts are immediately disabled. non-maskable interrupts are not affected by this instruction.
45 chapter 5 instruction divh divide half-word instruction format divh reg1, reg2 operation gr [reg2] ? gr [reg2] ? gr [reg1] format format i op code 15 0 rrrrr000010rrrrr flag cy C ov 1 if overflow occurs; otherwise, 0. s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction divh divide half-word explanation divides the word data of general register reg2 by the lower half-word data of general register reg1, and stores the quotient to general register reg2. if the data is divided by 0, overflow occurs, and the quotient is undefined. the data of general register reg1 is not affected. remark the remainder is not stored. overflow occurs when the maximum negative value (80000000h) is divided by C1 (in which case the quotient is 80000000h) and when data is divided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruction is executed, division is aborted, and the interrupt is processed. upon returning from the interrupt, the division is restarted from the beginning, with the return address being the address of this instruction. also, general registers reg1 and reg2 will retain their original values prior to the start of execution. the higher 16 bits of general register reg1 are ignored when division is executed.
chapter 5 instruction 46 ei enable interrupt instruction format ei operation psw.id ? 0 (enables maskable interrupt) format format x op code 15 0 31 16 1000011111100000 0000000101100000 flag cy C ov C sC zC sat C id 0 instruction ei enable interrupt explanation resets the id flag of the psw to 0 and enables the acknowledgement of maskable interrupts beginning at the next instruction. remark interrupts are not sampled during instruction execution.
47 chapter 5 instruction halt halt instruction format halt operation. halts format format x op code 15 0 31 16 0000011111100000 0000000100100000 flag cy C ov C sC zC sat C instruction halt halt explanation stops the operating clock of the cpu and places the cpu in the halt mode. remark the halt mode is exited by any of the following three events: ? reset input ? nmi input ? maskable interrupt (when id of psw = 0) if an interrupt is acknowledged during the halt mode, the address of the following instruction is stored to eipc or fepc.
chapter 5 instruction 48 jarl jump and register link instruction format jarl disp22, reg2 operation gr [reg2] ? pc + 4 pc ? pc + sign-extend (disp22) format format v op code 15 0 31 16 rrrrr11110dddddd ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. flag cy C ov C sC zC sat C instruction jarl jump and register link explanation saves the current pc value plus 4 to general register reg2, adds the current pc value and 22- bit displacement, sign-extended to word length, and transfers control to that pc. bit 0 of the 22-bit displacement is masked to 0. remark the current pc value used for calculation is the address of the first byte of this instruction. if the displacement value is 0, the branch destination is this instruction itself. this instruction is equivalent to a call subroutine instruction, and saves the pc return address to general register reg2. the jmp instruction, which is equivalent to a subroutine-return instruction, can be used to specify the general register containing the return address saved during the jarl subroutine-call instruction, to restore the program counter.
49 chapter 5 instruction jmp jump register instruction format jmp [reg1] operation pc ? gr [reg1] format format i op code 15 0 00000000011rrrrr flag cy C ov C sC zC sat C instruction jmp jump register explanation transfers control to the address specified by general register reg1. bit 0 of the address is masked to 0. remark when using this instruction as the subroutine-return instruction, specify the general register containing the return address saved during the jarl subroutine-call instruction, to restore the program counter. when using the jarl instruction, which is equivalent to the subroutine-call instruction, store the pc return address in general register reg2.
chapter 5 instruction 50 jr jump relative instruction format jr disp22 operation pc ? pc + sign-extend (disp22) format format v op code 15 0 31 16 0000011110dddddd ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. flag cy C ov C sC zC sat C instruction jr jump relative explanation adds the 22-bit displacement, sign-extended to word length, to the current pc value and stores the value in the pc, and then transfers control to that pc. bit 0 of the 22-bit displacement is masked to 0. remark the current pc value used for the calculation is the address of the first byte of this instruction itself. therefore, if the displacement value is 0, the jump destination is this instruction.
51 chapter 5 instruction ld load instruction format (1) ld.b disp16 [reg1], reg2 (2) ld.h disp16 [reg1], reg2 (3) ld.w disp16 [reg1], reg2 operation (1) adr ? gr [reg1] + sign-extend (disp16) gr [reg2] ? sign-extend (load-memory (adr, byte)) (2) adr ? gr [reg1] + sign-extend (disp16) gr [reg2] ? sign-extend (load-memory (adr, halfword)) (3) adr ? gr [reg1] + sign-extend (disp16) gr [reg2] ? load-memory (adr, word) format format vii op code 15 0 31 16 (1) rrrrr111000rrrrr dddddddddddddddd 15 0 31 16 (2) rrrrr111001rrrrr ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. 15 0 31 16 (3) rrrrr111001rrrrr ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. flag cy C ov C sC zC sat C instruction (1) ld.b load byte (2) ld.h load half-word (3) ld.w load word
chapter 5 instruction 52 explanation (1) adds the data of general register reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. byte data is read from the generated address, sign- extended to word length, and then stored to general register reg2. (2) adds the data of general register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. half-word data is read from this 32-bit address with its bit 0 masked to 0, sign-extended to word length, and stored to general register reg2. (3) adds the data of general register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored to general register reg2. caution when the data of general register reg1 is added to a 16-bit displacement sign-extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word) to generate an address.
53 chapter 5 instruction ldsr load to system register instruction format ldsr reg2, regid operation sr [regid] ? gr [reg2] format format ix op code 15 0 31 16 rrrrr111111rrrrr 0000000000100000 remark the fields used to define reg1 and reg2 are swapped in this instruction. normally, "rrr" is used for reg1 and is the source operand while rrr signifies reg2 and is the destination operand. in this instruction, rrr is still the source operand, but is represented by reg2, while rrr is the special register destination, as labeled below: rrrrr: regid specification rrrrr: reg2 specification flag cy C (refer to remark below.) ov C (refer to remark below.) s C (refer to remark below.) z C (refer to remark below.) sat C (refer to remark below.) instruction ldsr load to system register explanation loads the word data of general register reg2 to a system register specified by the system register number (regid). the data of general register reg2 is not affected. remark if the system register number (regid) is equal to 5 (psw register), the values of the corresponding bits of the psw are set according to the contents of reg2. this only affects the flag bits, the reserved bits remain at 0. also, interrupts are not sampled when the psw is being written with a new value. if the id flag is enabled with this instruction, interrupt disabling begins at the start of execution, even though the id flag does not become valid until the beginning of the next instruction. caution the system register number regid is a number which identifies a system register. accessing system registers which are reserved or write-prohibited is prohibited and will lead to undefined results.
chapter 5 instruction 54 mov move instruction format (1) mov reg1, reg2 (2) mov imm5, reg2 operation (1) gr [reg2] ? gr [reg1] (2) gr [reg2] ? sign-extend (imm5) format (1) format i (2) format ii op code 15 0 (1) rrrrr000000rrrrr 15 0 (2) rrrrr010000iiiii flag cy C ov C sC zC sat C instruction (1) mov move register (2) mov move immediate (5-bit) explanation (1) transfers the word data of general register reg1 to general register reg2. the data of general register reg1 is not affected. (2) transfers the value of a 5-bit immediate data, sign-extended to word length, to general register reg2.
55 chapter 5 instruction movea moves effective address instruction format movea imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] + sign-extend (imm16) format format vi op code 15 0 31 16 rrrrr110001rrrrr iiiiiiiiiiiiiiii flag cy C ov C sC zC sat C instruction movea move effective address explanation adds the 16-bit immediate data, sign-extended to word length, to the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected. the flags are not affected by the addition. remark this instruction calculates a 32-bit address and stores the result without affecting the psw flags.
chapter 5 instruction 56 movhi move high half-word instruction format movhi imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] + (imm16 ii 0 16 ) format format vi op code 15 0 31 16 rrrrr110010rrrrr iiiiiiiiiiiiiiii flag cy C ov C sC zC sat C instruction movhi move high half-word explanation adds a word value, whose higher 16 bits are specified by the 16-bit immediate data and lower 16 bits are 0, to the word data of general register reg1 and stores the result in general register reg2. the data of general register reg1 is not affected. the flags are not affected by the addition. remark this instruction is used to generate the high 16 bits of a 32-bit address.
57 chapter 5 instruction mulh multiply half-word instruction format (1) mulh reg1, reg2 (2) mulh imm5, reg2 operation (1) gr [reg2] (32) ? gr [reg2] (16) gr [reg1] (16) (2) gr [reg2] ? gr [reg2] sign-extend (imm5) format (1) format i (2) format ii op code 15 0 (1) rrrrr000111rrrrr 15 0 (2) rrrrr010111iiiii flag cy C ov C sC zC sat C instruction (1) mulh multiply half-word by register (2) mulh multiply half-word by immediate (5-bit) explanation (1) multiplies the lower half-word data of general register reg2 by the half-word data of general register reg1, and stores the result to general register reg2 as word data. the data of general register reg1 is not affected. (2) multiplies the lower half-word data of general register reg2 by a 5-bit immediate data, sign- extended to half-word length, and stores the result to general register reg2. remark the higher 16 bits of general registers reg1 and reg2 are ignored in this operation.
chapter 5 instruction 58 mulhi multiply half-word immediate instruction format mulhi imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] imm16 format format vi op code 15 0 31 16 rrrrr110111rrrrr iiiiiiiiiiiiiiii flag cy C ov C sC zC sat C instruction mulhi multiply half-word by immediate (16-bit) explanation multiplies the lower half-word data of general register reg1 by the 16-bit immediate data, and stores the result to general register reg2. the data of general register reg1 is not affected. remark the higher 16 bits of general register reg1 are ignored in this operation.
59 chapter 5 instruction nop no operation instruction format nop operation executes nothing and consumes at least one clock. format format i op code 15 0 0000000000000000 flag cy C ov C sC zC sat C instruction nop no operation explanation executes nothing and consumes at least one clock cycle. remark the contents of the pc are incremented by two. the op code is the same as that of mov r0, r0.
chapter 5 instruction 60 not not instruction format not reg1, reg2 operation gr [reg2] ? not (gr [reg1]) format format i op code 15 0 rrrrr000001rrrrr flag cy C ov C s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction not not explanation logically negates (takes the 1s complement of) the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected.
61 chapter 5 instruction not1 not bit instruction format not1 bit#3, disp16 [reg1] operation adr ? gr [reg1] + sign-extend (disp16) z flag ? not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) format format viii op code 15 0 31 16 01bbb111110rrrrr dddddddddddddddd flag cy C ov C sC z 1 if bit no.bit#3 of memory disp16 [reg1] = 0. 0 if bit no.bit#3 of memory disp16 [reg1] = 1. sat C instruction not1 not bit explanation adds the data of general register reg1 to a 16-bit displacement, sign-extended to word length to generate a 32-bit address. the bit, specified by the 3-bit field bbb, is inverted at the byte data location referenced by the generated address. the bits other than the specified bit are not affected. remark the z flag of the psw indicates whether the specified bit was 0 or 1 before this instruction is executed, and does not indicate the content of the specified bit after this instruction has been executed.
chapter 5 instruction 62 or or instruction format or reg1, reg2 operation gr [reg2] ? gr [reg2] or gr [reg1] format format i op code 15 0 rrrrr001000rrrrr flag cy C ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction or or explanation ors the word data of general register reg2 with the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected.
63 chapter 5 instruction ori or immediate instruction format ori imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] or zero-extend (imm16) format format vi op code 15 0 31 16 rrrrr110100rrrrr iiiiiiiiiiiiiiii flag cy C ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction or or immediate (16-bit) explanation ors the word data of general register reg1 with the value of the 16-bit immediate data, zero- extended to word length, and stores the result to general register reg2. the data of general register reg1 is not affected.
chapter 5 instruction 64 reti return from trap or interrupt instruction format reti operation if psw.ep = 1 then pc ? eipc psw ? eipsw else if psw.np = 1 then pc ? fepc psw ? fepsw else pc ? eipc psw ? eipsw format format x op code 15 0 31 16 0000011111100000 0000000101000000 flag cy value read from fepsw or eipsw is restored. ov value read from fepsw or eipsw is restored. s value read from fepsw or eipsw is restored. z value read from fepsw or eipsw is restored. sat value read from fepsw or eipsw is restored. instruction reti return from trap or interrupt explanation this instruction restores the return pc and psw from the appropriate system register and returns from an exception or interrupt routine. the operations of this instruction are as follows: (1) if the ep flag of the psw is 1, the return pc and psw are read from the eipc and eipsw, regardless of the status of the np flag of the psw. if the ep flag of the psw is 0 and the np flag of the psw is 1, the return pc and psw are read from the fepc and fepsw. if the ep flag of the psw is 0 and the np flag of the psw is 0, the return pc and psw are read from the eipc and eipsw. (2) once the pc and psw are restored to the return values, control is transferred to the return address.
65 chapter 5 instruction caution when returning from an nmi or exception routine using the reti instruction, the psw.np and psw.ep flags must be set accordingly to restore the pc and psw: ? when returning from non-maskable interrupt routine using the reti instruction: psw.np = 1 and psw.ep = 0 ? when returning from an exception routine using the reti instruction: psw.ep = 1 use the ldsr instruction for setting the flags. all interrupts are not accepted in the latter half of the id stage during ldsr execution because of the operation of the interrupt controller.
chapter 5 instruction 66 sar shift arithmetic right instruction format (1) sar reg1, reg2 (2) sar imm5, reg2 operation (1) gr [reg2] ? gr [reg2] arithmetically shift right by gr [reg1] (2) gr [reg2] ? gr [reg2] arithmetically shift right by zero-extend format (1) format ix (2) format ii op code 15 0 31 16 (1) rrrrr111111rrrrr 0000000010100000 15 0 (2) rrrrr010101iiiii flag cy 1 if the bit shifted out last is 1; otherwise, 0. however, if the number of shifts is 0, the result is 0. ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction (1) sar shift arithmetic right by register (2) sar shift arithmetic right by immediate (5-bit) explanation (1) arithmetically shifts the word data of general register reg2 to the right by n positions, where n is a value from 0 to +31, specified by the lower 5 bits of general register reg1 (after the shift, the msb prior to shift execution is copied and set as the new msb value), and then writes the result to general register reg2. if the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. the data of general register reg1 is not affected. (2) arithmetically shifts the word data of general register reg2 to the right by n positions, where n is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (after the shift, the msb prior to shift execution is copied and set as the new msb value), and then writes the result to general register reg2. if the number of shifts is 0, general register reg2 retains the same value prior to instruction execution.
67 chapter 5 instruction satadd saturated add instruction format (1) satadd reg1, reg2 (2) satadd imm5, reg2 operation (1) gr [reg2] ? saturated (gr [reg2] + gr [reg1]) (2) gr [reg2] ? saturated (gr [reg2] + sign-extend (imm5)) format (1) format i (2) format ii op code 15 0 (1) rrrrr000110rrrrr 15 0 (2) rrrrr010001iiiii flag cy 1 if a carry occurs from msb; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the saturated operation is negative; otherwise, 0. z 1 if the result of the saturated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. instruction (1) satadd saturated add register (2) satadd saturated add immediate (5-bit) explanation (1) adds the word data of general register reg1 to the word data of general register reg2, and stores the result to general register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored to reg2; if the result exceeds the maximum negative value 80000000h, 80000000h is stored to reg2. the sat flag is set to 1. the data of general register reg1 is not affected. (2) adds a 5-bit immediate data, sign-extended to word length, to the word data of general register reg2, and stores the result to general register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored to reg2; if the result exceeds the maximum negative value 80000000h, 80000000h is stored to reg2. the sat flag is set to 1. remark the sat flag is a cumulative flag. once the result of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operation is not saturated. even if the sat flag is set to 1, the saturated operation instruction is executed normally. caution to reset the sat flag to 0, load data to the psw by using the ldsr instruction.
chapter 5 instruction 68 satsub saturated subtract instruction format satsub reg1, reg2 operation gr [reg2] ? saturated (gr [reg2] C gr [reg1]) format format i op code 15 0 rrrrr000101rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the saturated operation is negative; otherwise, 0. z 1 if the result of the saturated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. instruction satsub saturated subtract explanation subtracts the word data of general register reg1 from the word data of general register reg2, and stores the result to general register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored to reg2; if the result exceeds the maximum negative value 80000000h, 80000000h is stored to reg2. the sat flag is set to 1. the data of general register reg1 is not affected. remark the sat flag is a cumulative flag. once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operations is not saturated. even if the sat flag is set to 1, the saturated operation instruction is executed normally. caution to reset the sat flag to 0, load data to the psw by using the ldsr instruction.
69 chapter 5 instruction satsubi saturated subtract immediate instruction format satsubi imm16, reg1, reg2 operation gr [reg2] ? saturated (gr [reg1] C sign-extend (imm16)) format format vi op code 15 0 31 16 rrrrr110011rrrrr iiiiiiiiiiiiiiii flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the saturated operation is negative; otherwise, 0. z 1 if the result of the saturated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. instruction satsubi saturated subtract immediate explanation subtracts the 16-bit immediate data, sign-extended to word length, from the word data of general register reg1, and stores the result to general register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored to reg2; if the result exceeds the maximum negative value 80000000h, 80000000h is stored to reg2. the sat flag is set to 1. the data of general register reg1 is not affected. remark the sat flag is a cumulative flag. once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operations is not saturated. even if the sat flag is set to 1, the saturated operation instruction is executed normally. caution to reset the sat flag to 0, load data to the psw by using the ldsr instruction.
chapter 5 instruction 70 satsubr saturated subtract reverse instruction format satsubr reg1, reg2 operation gr [reg2] ? saturated (gr [reg1] C gr [reg2]) format format i op code 15 0 rrrrr000100rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the saturated operation is negative; otherwise, 0. z 1 if the result of the saturated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. instruction satsubr saturated subtract reverse explanation subtracts the word data of general register reg2 from the word data of general register reg1, and stores the result to general register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored to reg2; if the result exceeds the maximum negative value 80000000h, 80000000h is stored to reg2. the sat flag is set to 1. the data of general register reg1 is not affected. remark the sat flag is a cumulative flag. once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operations is not saturated. even if the sat flag is set to 1, the saturated operation instruction is executed normally. caution to reset the sat flag to 0, load data to the psw by using the ldsr instruction.
71 chapter 5 instruction setf set flag condition instruction format setf cccc, reg2 operation if conditions are satisfied then gr [reg2] ? 00000001h else gr [reg2] ? 00000000h format format ix op code 15 0 31 16 rrrrr1111110cccc 0000000000000000 flag cy C ov C sC zC sat C instruction setf set flag condition explanation the general register reg2 is set to 1 if a condition specified by condition code cccc is satisfied; otherwise, 0 are stored to the register. one of the codes shown in table 5-9 should be specified as the condition code cccc. remark here are some examples of using this instruction: (1) translation of two or more condition clauses: if a of statement if (a) in c language consists of two or more condition clauses (a 1 , a 2 , a 3 , and so on), it is usually translated to a sequence of if (a 1 ) then, if (a 2 ) then. the object code executes conditional branch by checking the result of evaluation equivalent to a n . a pipeline processor takes more time to execute condition judgment + branch than to execute an ordinary operation, the result of evaluating each condition clause if (a n ) is stored to register ra. by performing a logical operation to ra n after all the condition clauses have been evaluated, the delay due to the pipeline can be prevented. (2) double-length operation: to execute a double-length operation such as add with carry, the result of the cy flag can be stored to general register reg2. therefore, a carry from the lower bits can be expressed as a numeric value.
chapter 5 instruction 72 table 5-9. condition codes condition code condition name condition expression (cccc) 0000 v ov = 1 1000 nv ov = 0 0001 c/l cy = 1 1001 nc/nl cy = 0 0010 z z = 1 1010 nz z = 0 0011 nh (cy or z) = 1 1011 h (cy or z) = 0 0100 s/n s = 1 1100 ns/p s = 0 0101 t always 1101 sa sat = 1 0110 lt (s xor ov) = 1 1110 ge (s xor ov) = 0 0111 le ((s xor ov) or z) = 1 1111 gt ((s xor ov) or z) = 0
73 chapter 5 instruction set1 set bit instruction format set1 bit#3, disp16 [reg1] operation adr ? gr [reg1] + sign-extend (disp16) z flag ? not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 1) format format viii op code 15 0 31 16 00bbb111110rrrrr dddddddddddddddd flag cy C ov C sC z 1 when bit no.bit#3 of memory disp16 [reg1] = 0. 0 when bit no.bit#3 of memory disp16 [reg1] = 1 sat C instruction set1 set bit explanation adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address. the bit, specified by the 3-bit field bbb, is set at the byte data location referenced by the generated address. the bits other than the specified bit are not affected. remark the z flag of the psw indicates whether the specified bit was 0 or 1 before this instruction is executed, and does not indicate the content of the specified bit after this instruction has been executed.
chapter 5 instruction 74 shl shift logical left instruction format (1) shl reg1, reg2 (2) shl imm5, reg2 operation (1) gr [reg2] ? gr [reg2] logically shift left by gr [reg1] (2) gr [reg2] ? gr [reg2] logically shift left by zero-extend (imm5) format (1) format ix (2) format ii op code 15 0 31 16 (1) rrrrr111111rrrrr 0000000011000000 15 0 (2) rrrrr010110iiiii flag cy 1 if the bit shifted out last is 1; otherwise, 0. however, if the number of shifts is 0, the result is 0. ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction (1) shl shift logical left by register (2) shl shift logical left by immediate (5-bit) explanation (1) logically shifts the word data of general register reg2 to the left by n positions, where n is a value from 0 to +31, specified by the lower 5 bits of general register reg1 (0 is shifted to the lsb side), and then writes the result to general register reg2. if the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. the data of general register reg1 is not affected. (2) logically shifts the word data of general register reg2 to the left by n positions, where n is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (0 is shifted to the lsb side), and then writes the result to general register reg2. if the number of shifts is 0, general register reg2 retains the value prior to instruction execution.
75 chapter 5 instruction shr shift logical right instruction format (1) shr reg1, reg2 (2) shr imm5, reg2 operation (1) gr [reg2] ? gr [reg2] logically shift right by gr [reg1] (2) gr [reg2] ? gr [reg2] logically shift right by zero-extend (imm5) format (1) format ix (2) format ii op code 15 0 31 16 (1) rrrrr111111rrrrr 0000000010000000 15 0 (2) rrrrr010100iiiii flag cy 1 if the bit shifted out last is 1; otherwise, 0. however, if the number of shifts is 0,the result is 0. ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction (1) shr shift logical right by register (2) shr shift logical right by immediate (5-bit) explanation (1) logically shifts the word data of general register reg2 to the right by n positions where n is a value from 0 to +31, specified by the lower 5 bits of general register reg1 (0 is shifted to the msb side). this instruction then writes the result to general register reg2. if the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. the data of general register reg1 is not affected. (2) logically shifts the word data of general register reg2 to the right by n positions, where n is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (0 is shifted to the msb side). this instruction then writes the result to general register reg2. if the number of shifts is 0, general register reg2 retains the same value prior to instruction execution.
chapter 5 instruction 76 sld load instruction format (1) sld.b disp7 [ep], reg2 (2) sld.h disp8 [ep], reg2 (3) sld.w disp8 [ep], reg2 operation (1) adr ? ep + zero-extend (disp7) gr [reg2] ? sign-extend (load-memory (adr, byte)) (2) adr ? ep + zero-extend (disp8) gr [reg2] ? sign-extend (load-memory (adr, halfword)) (2) adr ? ep + zero-extend (disp8) gr [reg2] ? load-memory (adr, word) format format iv op code 15 0 (1) rrrrr0110ddddddd 15 0 (2) rrrrr1000ddddddd ddddddd is the higher 7 bits of disp8. 15 0 (3) rrrrr1010dddddd0 dddddd is the higher 6 bits of disp8. flag cy C ov C sC zC sat C instruction (1) sld.b short format load byte (2) sld.h short format load half-word (3) sld.w short format load word
77 chapter 5 instruction explanation (1) adds the 7-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. byte data is read from the generated address, sign-extended to word length, and stored to reg2. (2) adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. half-word data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored to reg2. (3) adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored to reg2. caution when the element pointer is added to the 8-bit displacement zero extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word).
chapter 5 instruction 78 sst short store instruction format (1) sst.b reg2, disp7 [ep] (2) sst.h reg2, disp8 [ep] (3) sst.w reg2, disp8 [ep] operation (1) adr ? ep + zero-extend (disp7) store-memory (adr, gr [reg2], byte) (2) adr ? ep + zero-extend (disp8) store-memory (adr, gr [reg2], halfword) (2) adr ? ep + zero-extend (disp8) store-memory (adr, gr [reg2], word) format format iv op code 15 0 (1) rrrrr0111ddddddd 15 0 (2) rrrrr1001ddddddd ddddddd is the higher 7 bits of disp8. 15 0 (3) rrrrr1010dddddd1 dddddd is the higher 6 bits of disp8. flag cy C ov C sC zC sat C instruction (1) sst.b short format store byte (2) sst.h short format store half-word (3) sst.w short format store word
79 chapter 5 instruction explanation (1) adds the 7-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 to the generated address. (2) adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower half-word data of reg2 to the generated 32-bit address with bit 0 masked to 0. (3) adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 to the generated 32-bit address with bits 0 and 1 masked to 0. caution when the element pointer is added to the 8-bit displacement zero-extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word).
chapter 5 instruction 80 st store instruction format (1) st.b reg2, disp16 [reg1] (2) st.h reg2, disp16 [reg1] (3) st.w reg2, disp16 [reg1] operation (1) adr ? gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], byte) (2) adr ? gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], halfword) (2) adr ? gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], word) format format vii op code 15 0 31 16 (1) rrrrr111010rrrrr dddddddddddddddd 15 0 31 16 (2) rrrrr111011rrrrr ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. 15 0 31 16 (3) rrrrr111011rrrrr ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. flag cy C ov C sC zC sat C instruction (1) st.b store byte (2) st.h store half-word (3) st.w store word
81 chapter 5 instruction explanation (1) adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address, and stores the lowest byte data of general register reg2 to the generated address. (2) adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address, and stores the lower half-word data of general register reg2 to the generated 32-bit address with bit 0 masked to 0. therefore, stored data is automatically aligned on a half-word boundary. (3) adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address, and stores the word data of general register reg2 to the generated 32-bit address with bits 0 and 1 masked to 0. therefore, stored data is automatically aligned on a word boundary. caution when the data of general register reg1 is added to a 16-bit displacement sign-extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word) to generate an address.
chapter 5 instruction 82 stsr store contents of system register instruction format stsr regid, reg2 operation gr [reg2] ? sr [regid] format format ix op code 15 0 31 16 rrrrr111111rrrrr 0000000001000000 flag cy C ov C sC zC sat C instruction stsr store contents of system register explanation stores the contents of a system register specified by system register number (regid) to general register reg2. the contents of the system register are not affected. remark the system register number regid is a number which identifies a system register. accessing system register which is reserved is prohibited and will lead to undefined results.
83 chapter 5 instruction sub subtract instruction format sub reg1, reg2 operation gr [reg2] ? gr [reg2] C [reg1] format format i op code 15 0 rrrrr001101rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction sub subtract explanation subtracts the word data of general register reg1 from the word data of general register reg2, and stores the result to general register reg2. the data of general register reg1 is not affected.
chapter 5 instruction 84 subr subtract reverse instruction format subr reg1, reg2 operation gr [reg2] ? gr [reg1] C gr [reg2] format format i op code 15 0 rrrrr001100rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction subr subtract reverse explanation subtracts the word data of general register reg2 from the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected.
85 chapter 5 instruction trap software trap instruction format trap vector operation eipc ? pc + 4 (return pc) eipsw ? psw ecr.eicc ? interrupt code psw.ep ? 1 psw.id ? 1 pc ? 00000040h (vector = 00h-0fh) 00000050h (vector = 10h-1fh) format format x op code 15 0 31 16 00000111111iiiii 0000000100000000 flag cy C ov C sC zC sat C instruction trap trap explanation saves the return pc and psw to eipc and eipsw, respectively; sets the exception code (eicc of ecr) and the flags of the psw (ep and id flags); jumps to the address of the trap handler corresponding to the trap vector specified by vector number (0-31), and starts exception processing. the condition flags are not affected. the return pc is the address of the instruction following the trap instruction.
chapter 5 instruction 86 tst test instruction format tst reg1, reg2 operation result ? gr [reg2] and gr [reg1] format format i op code 15 0 rrrrr001011rrrrr flag cy C ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction tst test explanation ands the word data of general register reg2 with the word data of general register reg1. the result is not stored, and only the flags are changed. the data of general registers reg1 and reg2 are not affected.
87 chapter 5 instruction tst1 test bit instruction format tst1 bit#3, disp16 [reg1] operation adr ? gr [reg1] + sign-extend (disp16) z flag ? not (load-memory-bit (adr,bit#3)) format format viii op code 15 0 31 16 11bbb111110rrrrr dddddddddddddddd flag cy C ov C sC z 1 if bit no.bit#3 of memory disp16 [reg1] = 0. 0 if bit no.bit#3 of memory disp16 [reg1] = 1. sat C instruction tst1 test bit explanation adds the data of general register reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. performs the test on the bit, specified by the 3-bit field bbb, at the byte data location referenced by the generated address. if the specified bit is 0, the z flag is set to 1; if the bit is 1, the z flag is reset to 0. the byte data, including the specified bit, is not affected.
chapter 5 instruction 88 xor exclusive or instruction format xor reg1, reg2 operation gr [reg2] ? gr [reg2] xor gr [reg1] format format i op code 15 0 rrrrr001001rrrrr flag cy C ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction xor exclusive or explanation exclusively ors the word data of general register reg2 with the word data of general register reg1, and stores the result to general register reg2. the data of general register reg1 is not affected.
89 chapter 5 instruction xori exclusive or immediate instruction format xori imm16, reg1, reg2 operation gr [reg2] ? gr [reg1] xor zero-extend (imm16) format format vi op code 15 0 31 16 rrrrr110101rrrrr iiiiiiiiiiiiiiii flag cy C ov 0 s 1 if the result of an operation is negative; otherwise, 0. z 1 if the result of an operation is 0; otherwise, 0. sat C instruction xori exclusive or immediate (16-bit) explanation exclusively ors the word data of general register reg1 with a 16-bit immediate data, zero- extended to word length, and stores the result to general register reg2. the data of general register reg1 is not affected.
chapter 5 instruction 90 5.4 number of instruction execution clock cycles the number of instruction execution clock cycles differ depending on the combination of instructions. for details, refer to chapter 8 pipeline . table 5-10 shows a list of the number of instruction execution clock cycles. table 5-10. list of number of instruction execution clock cycles (1/3) instructions mnemonic operand byte execution clock i C r C l load/store sld.b disp7 [ep], r 2 1 C 1 C 2 sld.h disp8 [ep], r 2 1 C 1 C 2 sld.w disp8 [ep], r 2 1 C 1 C 2 sst.b r, disp7 [ep] 2 1 C 1 C 1 sst.h r, disp8 [ep] 2 1 C 1 C 1 sst.w r, disp8 [ep] 2 1 C 1 C 1 ld.b disp16 [r], r 4 1 C 1 C 2 ld.h disp16 [r], r 4 1 C 1 C 2 ld.w disp16 [r], r 4 1 C 1 C 2 st.b r, disp16 [r] 4 1 C 1 C 1 st.h r, disp16 [r] 4 1 C 1 C 1 st.w r, disp16 [r] 4 1 C 1 C 1 arithmetic mov r, r 2 1 C 1 C 1 operation mov imm5, r 2 1 C 1 C 1 movea imm16, r, r 4 1 C 1 C 1 movhi imm16, r, r 4 1 C 1 C 1 divh r, r 2 36 C 36 C 36 mulh r, r 2 1 C 1 C 2 mulh imm5, r 2 1 C 1 C 2 mulhi imm16, r, r 4 1 C 1 C 2 add r, r 2 1 C 1 C 1 add imm5, r 2 1 C 1 C 1 addi imm16, r, r 4 1 C 1 C 1 cmp r, r 2 1 C 1 C 1 cmp imm5, r 2 1 C 1 C 1 subr r, r 2 1 C 1 C 1 sub r, r 2 1 C 1 C 1 setf cccc, r 4 1 C 1 C 1 saturated satsubr r, r 2 1 C 1 C 1 operation satsub r, r 2 1 C 1 C 1 satadd r, r 2 1 C 1 C 1 satadd imm5, r 2 1 C 1 C 1 satsubi imm16, r, r 4 1 C 1 C 1
91 chapter 5 instruction table 5-10. list of number of instruction execution clock cycles (2/3) instructions mnemonic operand byte execution clock i C r C l logical not r, r 2 1 C 1 C 1 operation or r, r 2 1 C 1 C 1 xor r, r 2 1 C 1 C 1 and r, r 2 1 C 1 C 1 tst r, r 2 1 C 1 C 1 shr imm5, r 2 1 C 1 C 1 sar imm5, r 2 1 C 1 C 1 shl imm5, r 2 1 C 1 C 1 ori imm16, r, r 4 1 C 1 C 1 xori imm16, r, r 4 1 C 1 C 1 andi imm16, r, r 4 1 C 1 C 1 shr r, r 4 1 C 1 C 1 sar r, r 4 1 C 1 C 1 shl r, r 4 1 C 1 C 1 branch jmp [r] 2 3 C 3 C 3 jr disp22 4 3 C 3 C 3 jarl disp22, r 4 3 C 3 C 3 bcond disp9 when condition is satisfied 2 3 C 3 C 3 when condition is not satisfied 2 1 C 1 C 1 bit set1 bit#3, disp16 [r] 4 4 C 4 C 4 manipulation clr1 bit#3, disp16 [r] 4 4 C 4 C 4 not1 bit#3, disp16 [r] 4 4 C 4 C 4 tst1 bit#3, disp16 [r] 4 3 C 3 C 3 special ldsr r, sr 4 1 C 1 C note stsr sr, r 4 1 C 1 C 1 nop C 2 1 C 1 C 1 di C 4 1 C 1 C 1 ei C 4 1 C 1 C 1 trap vector 4 4 C 4 C 4 halt C 4 1 C 1 C 1 reti C 4 4 C 4 C 4 undefined instruction code trap 4 4 C 4 C 4 note when accessing eipc, fepc: 3 when accessing eipsw, fepsw, psw: 1
chapter 5 instruction 92 table 5-10. list of number of instruction execution clock cycles (3/3) operand symbol meaning r: reg1 general register (used as source register) r: reg2 general register (mainly used as destination register) sr: system register system register imm : immediate -bit immediate disp : displacement -bit displacement bit#3: bit number 3-bit data for bit number specification ep: element pointer element pointer b: byte byte (8 bits) h: halfword half-word (16 bits) w: word word (32 bits) cccc: conditions 4-bit data condition code specification vector 5-bit data for trap vector (00h-1fh) specification execution clock symbol meaning i: issue when other instruction is executed immediately after executing an instruction r: repeat when the same instruction is repeatedly executed immediately after the instruction has been executed l: latency when a subsequent instruction uses the result of execution of the preceding instruction immediately after its execution
chapter 6 interrupt and exception interrupts are events that occur independently of the program execution and are divided into two types: maskable and non-maskable interrupts. in contrast, an exception is an event whose occurrence is dependent on the program execution. there is no major difference between the interrupt and exception in terms of control flow. however, the interrupt takes precedence over the exception. the v850 can process various interrupt requests from the on-chip peripheral hardware and external sources. in addition, exception processing can be started by an instruction (trap instruction) and by occurrence of an exception event (exception trap). the interrupts and exceptions supported in the v850 family are described below. when an interrupt or exception is deleted, control is transferred to a handler whose address is determined by the source of the interrupt or exception. the source of the event is specified by the exception code that is stored in the exception cause register (ecr). each handler analyzes the exception cause register (ecr) and performs appropriate interrupt servicing or exception handling. the return pc and psw are written to the status saving registers (eipc, eipsw/fepc, fepsw). to return execution from interrupt or exception processing, use the reti instruction. read the return pc and psw from the status saving register, and transfer control to the return pc. ? types of interrupt/exception processing the v850 family handles the following four types of interrupts/exceptions: ? non-maskable interrupt ? maskable interrupt ? software exception ? exception trap 93
chapter 6 interrupt and exception 94 table 6-1. interrupt/exception codes interrupt/exception cause classification exception code handler address return pc name trigger nmi nmi input interrupt 0010h 00000010h next pc note 2 maskable interrupt note 1 interrupt note 1 note 1 next pc note 2 trap0n (n = 0 - fh) trap instruction exception 004nh 00000040h next pc trap1n (n = 0 - fh) trap instruction exception 005nh 00000050h next pc ilgop illegal op code exception 006nh 00000060h next pc note 3 notes 1. differs depending on the type of the maskable interrupts. 2. if an interrupt is acknowledged during execution of a divh (divide) instruction, the restore pc becomes the pc value for the currently executed instruction (divh). 3. the execution address of the illegal instruction is obtained by retention pc-4 when an illegal op code exception occurs. the return pc is the pc saved to the eipc or fepc when interrupt/exception processing is started. next pc is the pc that starts processing after interrupt/exception processing. the processing of maskable interrupts is controlled by the user through the intc unit (interrupt controller). the intc is different for each device in the v850 family due to the variations of on-chip peripherals, interrupt/exception causes and exception codes. 6.1 interrupt servicing 6.1.1 maskable interrupt the maskable interrupt can be masked by the program status word (psw). the intc issues an interrupt request to the cpu, based on the accepted interrupt with the highest priority. if a maskable interrupt occurs due to int input, the processor performs the following steps, and transfers control to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower half-word of ecr (eicc). (4) sets id bit of psw and clears ep bit. (5) sets handler address for each interrupt to pc and transfers control. interrupts are held pending in the interrupt controller (intc) when one of the following two conditions occur: when the interrupt input (int) is masked by its intc, or when an interrupt service routine is currently being executed (when the np bit of the psw is 1 or when the id bit of the psw is 1). interrupts are enabled by clearing the mask condition and by resetting the np and id bits of the psw to 0 with the ldsr and reti instructions, which will be enabling servicing of a new or already pending interrupt. the eipc and eipsw are used as the status saving registers. these registers must be saved by program to enable nesting of interrupts because there is only one set of eipc and eipsw is provided. bits 31 through 24 of the eipc and bits 31 through 8 of the eipsw are fixed to 0. figure 6-1 illustrates how the maskable interrupt is serviced.
95 chapter 6 interrupt and exception figure 6-1. maskable interrupt servicing format mask psw.np psw.id eipc eipsw ecr.eicc psw.ep psw.id pc ? ? ? ? ? ? restore pc psw exception code 0 1 handler address yes 1 1 0 0 no maskable interrupt (int) occurs interrupt request pending interrupt servicing pending interrupt servicing
chapter 6 interrupt and exception 96 6.1.2 non-maskable interrupt the non-maskable interrupt cannot be disabled by an instruction and therefore can be always accepted. the non- maskable interrupt of the v850 family is generated by the nmi input. when the non-maskable interrupt is generated by the nmi input, the processor performs the following steps, and transfers control to the handler routine. (1) saves restore pc to fepc. (2) saves current psw to fepsw. (3) writes exception code to higher half-word of ecr (fecc). (4) sets np and id bits of psw and clears ep bit. (5) sets handler address (00000010h) for the non-maskable interrupt to pc and transfers control. non-maskable interrupts are held pending in the intc when other non-maskable interrupt is currently being executed (when the np bit of the psw is 1). non-maskable interrupts are enabled by resetting the np bit of the psw to 0 with the reti and ldsr instructions, which will be enabling servicing of a new or already pending interrupt. the fepc and fepsw are used as the status saving registers. figure 6-2 illustrates how the non-maskable interrupt is serviced. figure 6-2. non-maskable interrupt servicing format psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc ? ? ? ? ? ? ? restore pc psw exception code 1 0 1 00000010h 1 0 non-maskable interrupt (nmi) occurs interrupt servicing pending interrupt servicing
97 chapter 6 interrupt and exception 6.2 exception processing 6.2.1 software exception a software exception is generated when the cpu executes the trap instruction and is always accepted. if a software exception occurs, the cpu performs the following steps,and transfers control to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower 16 bits (eicc) of ecr (interrupt cause). (4) sets ep and id bits of psw. (5) sets handler address (00000040h or 00000050h) for software exception to pc and transfers control. figure 6-3 illustrates how the software exception is processed. figure 6-3. software exception processing format handler address: 00000040h (vector = 0nh) 00000050h (vector = 1nh) eipc eipsw ecr.eicc psw.ep psw.id pc ? ? ? ? ? ? restore pc psw exception code 1 1 handler address software exception (trap instruction) occurs exception processing
chapter 6 interrupt and exception 98 6.2.2 exception trap the exception trap is an interrupt requested when an instruction is illegally executed. the exception trap of the v850 family is generated by an illegal op code instruction code trap (ilgop: illegal opcode trap). an illegal op code instruction has an instruction code with an op code (bits 5 through 10) of 111111b and a sub- op code (bits 23 through 26) of 0011b through 1111b. when this kind of an illegal op code instruction is executed, an illegal op code instruction code trap occurs. figure 6-4. illegal instruction code remark : dont care : op code/sub-op code portion if an exception trap occurs, the cpu performs the following steps, and transfers control to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower 16 bits (eicc) of ecr. (4) sets ep and id bits of psw. (5) sets handler address (00000060h) for exception trap to pc and transfers control. figure 6-5 illustrates how the exception trap is processed. figure 6-5. exception trap processing format the execution address of the illegal instruction is obtained by restore pc - 4 when an exception trap occurs. caution in addition to the defined op codes and illegal op codes, there is a range of codes not recognized by this processor. if an instruction corresponding to these codes is executed, normal operation is undetermined. eipc eipsw ecr.eicc psw.ep psw.id pc ? ? ? ? ? ? restore pc psw exception code 1 1 00000060h exception trap (ilgop) occurs exception processing 001 1 111 1 15 13 12 11 10 5 4 0 31 27 26 23 22 21 20 17 16 111111
99 chapter 6 interrupt and exception 6.3 restoring from interrupt/exception all restoration from interrupt servicing/exception processing is executed by the reti instruction. with the reti instruction, the processor performs the following steps,and transfers control to the address of the restore pc. (1) if the ep bit of the psw is 0 and the np bit of the psw is 1, the restore pc and psw are read from the fepc and fepsw. otherwise, the restore pc and psw are read from the eipc and eipsw. (2) control is transferred to the address of the restored pc and psw. when execution has returned from exception processing or non-maskable interrupt servicing, the np and ep bits of the psw must be set to the following values by using the ldsr instruction immediately before the reti instruction, in order to restore the pc and psw normally: to restore from non-maskable interrupt np = 1, ep = 0 to restore from exception processing ep = 1 figure 6-6 illustrates how restoration from interrupt/exception is performed. figure 6-6. restoration from interrupt/exception psw.ep psw.np pc psw ? ? eipc eipsw 1 0 reti instruction jump to pc pc psw ? ? fepc fepsw 1 0 restoration from exception restoration from non-maskable interrupt restoration from maskable interrupt
[memo] 100
chapter 7 reset when a low-level signal is input to the reset pin, the system is reset, and each on-chip hardware is initialized. 7.1 initializing when a low-level signal is input to the reset pin, the system is reset, and each hardware register is set in the status shown in table 7-1. when the reset signal goes high, program execution begins. if necessary, re-initialize the contents of each register by program control. table 7-1. register status after reset hardware (symbol) status after reset program counter pc 00000000h interrupt status saving register eipc undefined eipsw undefined nmi status saving register fepc undefined fepsw undefined exception cause register (ecr) fecc 0000h eicc 0000h program status word psw 00000020h general register r0 fixed to 00000000h r1 - r31 undefined 7.2 starting up all devices in the v850 family begin program execution from address 00000000h after it has been reset. after reset, no immediate interrupt requests are accepted. to enable interrupts, clear the id bit of the program status word (psw) to 0. 101
[memo] 102
chapter 8 pipeline the v850 family is based on the risc architecture and executes almost all the instructions in one clock cycle under control of a 5-stage pipeline. the processor uses a 5-stage pipeline. the operation to be performed in each stage is as follows: if (instruction fetch) ............................................................ instruction is fetched and fetch pointer is incremented. id (instruction decode) ........................................................ instruction is decoded, immediate data is generated, and register is read. ex (execution of alu, multiplier, and barrel shifter) ......... the instruction is executed. mem (memory access) ....................................................... memory at specified address is accessed. wb (write back) ................................................................... result of execution is written to register. 8.1 outline of operation the instruction execution sequence of the v850 family consists of five stages including fetch and write back stages. the execution time of each stage differs depending on the type of the instruction and the type of the memory to be accessed. as an example of pipeline operation, figure 8-1 shows the processing of the cpu when nine standard instructions are executed in succession. figure 8-1. example of executing nine standard instructions 1 through 13 in the figure above indicate the states of the cpu. in each state, write back of instruction n, memory access of instruction n+1, execution of instruction n+2, decoding of instruction n+3, and fetching of instruction n+4 are simultaneously performed. it takes five clock cycles to process a standard instruction, including fetching and write back. because five instructions can be processed at the same time, however, a standard instruction can be executed in 1 clock cycle on the average. if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb 1 2 3 4 5 6 7 8 9 10 11 12 13 system clock instruction 1 instruction 2 instruction 3 instruction 4 instruction 5 instruction 6 instruction 7 instruction 8 instruction 9 time flow (state) processing cpu performs simultaneously end of instruc- tion 3 end of instruc- tion 4 end of instruc- tion 5 end of instruc- tion 6 end of instruc- tion 7 end of instruc- tion 8 end of instruc- tion 9 end of instruc- tion 2 end of instruc- tion 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? executes instruction every 1 clock cycle 103
chapter 8 pipeline 104 8.2 pipeline flow during execution of instructions this section explains the pipeline flow during the execution of instructions. during instruction fetch (if stage) and memory access (mem stage), the internal rom/prom and the internal ram are accessed, respectively. in this case, the if and mem stages are processed in 1 clock. in all other cases, the required time for access consists of the fixed access time, with the addition in some cases of the path wait time. access times are shown in figure 8-2 below. figure 8-2. access times (in clocks) resource (bus width) internal rom/prom internal ram internal peripheral i/o external memory stage (32 bits) (32 bits) (8/16 bits) (16 bits) instruction fetch 1 3 not possible 3 + n memory access (mem) 3 1 3 + n 3 + n remark n: wait number 8.2.1 load instructions [instructions] ld, sld [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. if an instruction using the execution result is placed immediately after the load instruction, data wait time occurs. for details, see 8.3 pipeline disorder . 8.2.2 store instructions [instructions] st, sst [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem and wb. however, no operation is performed in the wb stage, because no data is written to registers. 8.2.3 arithmetic operation instructions (excluding multiply and divide instructions) [instructions] mov, movea, movhi, add, addi, cmp, sub, subr, setf [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem and wb. however, no operation is performed in the mem stage, because memory is not accessed. if id ex mem wb if id ex mem wb load instruction next instruction 1234 56 store instruction next instruction if id ex mem wb if id ex mem wb 1234 56 if id ex mem wb if id ex mem wb arithmetic operation instruction next instruction 1234 56
105 chapter 8 pipeline 8.2.4 multiply instructions [instructions] mulh, mulhi [pipeline] (1) when next instruction is not multiply instruction (2) when next instruction is multiply instruction [description] the pipeline consists of 5 stages, if, id, ex1, ex2, and wb. there is no mem stage. the ex stage requires 2 clocks, but the ex1 and ex2 stages can operate independently. therefore, the number of clocks for instruction execution is always 1, even if several multiply instructions are executed in a row. however, if an instruction using the execution result is placed immediately after a multiply instruction, data wait time occurs. for details, see section 8.3 pipeline disorder . 8.2.5 divide instruction [instructions] divh [pipeline] C : idle inserted for wait [description] the pipeline consists of 40 stages, if, id, ex1 to ex36, mem, and wb. the ex stage requires 36 clocks. no operation is performed in the mem stage, because memory is not accessed. 8.2.6 logical operation instructions [instructions] not, or, ori, xor, xori, and, andi, tst, shr, sar, shl [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. no operation is performed in the mem stage, because memory is not accessed. if id ex1 ex2 wb if id ex mem wb multiply instruction next instruction 1234 56 multiply instruction 1 multiply instruction 2 if id ex1 ex2 wb if id ex1 ex2 wb 1234 56 1234 divide instruction next instruction if id ex1 ex2 if 38 39 40 ex35 ex36 mem wb id ex mem wb if id ex mem wb next to next instruction 37 41 42 if id ex mem wb if id ex mem wb logical operation instruction next instruction 1234 56
chapter 8 pipeline 106 8.2.7 saturation operation instructions [instructions] satadd, satsub, satsubi, satsubr [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the mem stage, because memory is not accessed. 8.2.8 branch instruction (1) conditional branch instructions [instructions] bcond instructions (bgt, bge, blt, ble, bh, bnl, bl, bnh, be, bne, bv, bnv, bn, bp, bc, bnc, bz, bnz, bsa): except br instruction [pipeline] (a) when the condition is not realized (b) when the condition is realized if : instruction fetch that is not executed id : instruction decode that is not executed [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memory is not accessed and no data is written to registers. (a) when the condition is not realized the number of execution clocks for the branch instruction is 1. (b) when the condition is realized the number of execution clocks for the branch instruction is 3. if stage of the next instruction and next to next instruction of the branch instruction is not executed. if id ex mem wb if id ex mem wb saturation operation instruction next instruction 1234 56 if id ex mem wb if id ex mem wb conditional branch instruction next instruction 1234 56 if id ex mem wb if id conditional branch instruction next instruction if id ex if mem wb next to next instruction branch destination instruction 1234 56 78
107 chapter 8 pipeline (2) unconditional branch instructions [instructions] jmp, jr, jarl, br [pipeline] if x : instruction fetch that is not executed wb note : no operation is performed in the case of the jmp instruction, jr instruction, and br instruction, but in the case of the jarl instruction, data is written to the restore pc. [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memory is not accessed and no data is written to registers. however, in the case of the jarl instruction, data is written to the restore pc in the wb stage. also, the if stage of the next instruction of the branch instruction is not executed. 8.2.9 bit manipulation instructions (1) set1, clr1, not1 [pipeline] C : idle inserted for wait [description] the pipeline consists of 8 stages, if, id, ex1, mem, ex2, ex3, mem, and wb. however, no operation is performed in the wb stage, because no data is written to registers. in the case of these instructions, the memory access is read modify write, and the ex and mem stages require 3 and 2 clocks, respectively. if id ex mem wb note if unconditional branch instruction next instruction if id ex mem wb branch destination instruction 1234 56 78 next instruction if id ex1 mem if id ex3 mem wb ex mem wb id ex mem wb next to next instruction ex2 if 1234 56 78 9 10 set1, clr1, not1 instruction
chapter 8 pipeline 108 (2) tst1 [pipeline] C : idle inserted for wait [description] the pipeline consists of 8 stages, if, id, ex1, mem, ex2, ex3, mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no second memory access nor data write to registers. in the case of this instruction, the memory access is read modify write, and the ex and mem stage require 3 and 2 clocks, respectively. 8.2.10 special instructions (1) ldsr, stsr [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the mem stage, because memory is not accessed. also, if the stsr instruction using the eipc and fepc system registers is placed immediately after the ldsr instruction setting these registers, data wait time occurs. for details, see section 8.3 pipeline disorder . (2) nop [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the ex, mem and wb stages, because no operation and no memory access is executed, and no data is written to registers. (3) ei, di [pipeline] [description] the pipeline consists of 5 stages, if, id, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memory is not accessed and data is not written to registers. tst1 instruction next instruction if id ex1 mem if id ex3 mem wb ex mem wb id ex mem wb next to next instruction ex2 if 1234 56 78 9 10 if id ex mem wb if id ex mem wb ldsr, stsr instruction next instruction 1234 56 if id ex if id ex mem wb nop instruction next instruction mem wb 1234 56 if id ex mem wb if id ex mem wb ei, di instruction next instruction 1234 56
109 chapter 8 pipeline (4) halt [pipeline] C : idle inserted for wait [description] the pipeline consists of 5 stages, if, id, ex, mem and wb. no operation is performed in the mem and wb stages, because memory is not accessed and no data is written to registers. also, for the next instruction, the id stage is delayed until the halt state is released. (5) trap [pipeline] if x : instruction fetch that is not executed id1 : trap code detect id2 : address generate [description] the pipeline consists of 6 stages, if, id1, id2, ex, mem, and wb. however, no operation is performed in the mem stage, because memory is not accessed. the id stage requires 2 clocks. also, the if stage of the next instruction and next to next instruction is not executed. (6) reti [pipeline] if x : instruction fetch that is not executed id1 : register select id2 : read eipc/fepc [description] the pipeline consists of 6 stages, if, id1, id2, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memory is not accessed and no data is written to registers. the id stage requires 2 clocks. also, the if stage of the next instruction and next to next instruction is not executed. if id1 id2 ex mem trap instruction next instruction 1234 56 wb if id ex mem wb 7 89 jump destination instruction if if id1 id2 ex mem if reti instruction next instruction 1234 56 wb if id ex mem wb 7 89 jump destination instruction if id ex mem if 1234 56 wb if id ex mem ?d ex mem wb wb halt instruction next instruction next to next instruction halt release
chapter 8 pipeline 110 8.3 pipeline disorder the pipeline consists of 5 stages from if (instruction fetch) to wb (write back). each stage basically requires 1 clock for processing, but the pipeline may become disordered, causing the number of execution clocks to increase. this section describes the main causes of pipeline disorder. 8.3.1 alignment hazard if the branch destination instruction address is not word aligned (a1=1, a0=0) and is 4 bytes in length, it is necessary to repeat if twice in order to align instructions in word units. this is called align hazard. for example, let us suppose that instructions a to e are placed from address x0h, and that instruction b consists of 4 bytes, and the other instructions each consist of 2 bytes. in this case, instruction b is placed at x2h (a1=1, a0=0), and is not word aligned (a1=0, a0=0). therefore, when this instruction b becomes the branch destination instruction, an align hazard occurs. when an align hazard occurs, the number of execution clocks of the branch instruction becomes 4. figure 8-3. align hazard example (a) memory map (b) pipeline if x : instruction fetch that is not executed C : idle inserted for wait if1 : first instruction fetch that occurs during align hazard. it is a 2-byte fetch that fetches the 2 bytes on the lower address of instruction b. if2 : second instruction fetch that occurs during align hazard. it is normally a 4-byte fetch that fetches the 2 bytes on the upper address of instruction b in addition to instruction c (2-byte length). align hazard can be prevented through the following handling in order to obtain faster instruction execution. ? use 2-byte branch destination instruction. ? use 4-byte instructions placed at word boundaries (a1=0, a0=0) for branch destination instructions. instruc- tion d instruc- tion e instruc- tion b instruc- tion c instruc- tion a instruc- tion b x8h x4h x0h 32 bits address of branch destination instruction (instruction b) if id ex mem wb if branch instruction next instruction next to next instruction 1234 56 78 if1 if2 id ex mem if wb if id ex mem wb 9 10 branch destination instruction (instruction b) branch destination? next instruction (instruction c)
111 chapter 8 pipeline 8.3.2 referencing execution result of load instruction for load instructions (ld, sld), data read in the mem stage is saved during the wb stage. therefore, if the contents of the same register are used by the instruction immediately after the load instruction, it is necessary to delay the use of the register by this later instruction until the load instruction has ended using that register. this is called a hazard . the v850 family has an interlock function that causes the cpu to automatically handle this hazard by delaying the id stage of the next instruction. the v850 family also has a short path that allows the data read during the mem stage to be used in the id stage of the next instruction. this short path allows data to be read with the load instruction during the mem stage and the use of this data in the id stage of the next instruction with the same timing. as a result of the above, when using the execution result in the instruction following immediately after, the number of execution clocks of the load instruction is 2. figure 8-4. example of execution result of load instruction il : idle inserted for data wait by interlock function C : idle inserted for wait : short path as described above, when an instruction placed immediately after a load instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. this drop in execution speed can be avoided by placing instructions that use the execution result of a load instruction at least 2 instructions after the load instruction. 8.3.3 referencing execution result of multiply instruction for multiply instructions (mulh, mulhi), the operation result is saved to the register in the wb stage. therefore, if the contents of the same register are used by the instruction immediately after the multiply instruction, it is necessary to delay the use of the register by this later instruction until the multiply instruction has ended using that register (occurrence of hazard). the v850 familys interlock function delays the id stage of the instruction following immediately after. a short path is also provided that allows the ex2 stage of the multiply instruction and the multiply instructions operation result to be used in the id stage of the instruction following immediately after with the same timing. figure 8-5. example of execution result of multiply instruction il : idle inserted for data wait by interlock function C : idle inserted for wait : short path if id ex mem wb if il id ex mem load instruction 1 (ld [r4], r6) instruction 2 (add 2, r6) wb if id ex mem if id ex mem wb wb instruction 3 instruction 4 1234 56 78 9 if id ex1 ex2 wb if il id ex mem instruction 2 (add 2, r6) wb if id ex mem if id ex mem wb wb instruction 3 instruction 4 1234 56 multiply instruction 1 (mulh 3, r6) 78 9
chapter 8 pipeline 112 as described above, when an instruction placed immediately after a multiply instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. this drop in execution speed can be avoided by placing instructions that use the execution result of a multiply instruction at least 2 instructions after the multiply instruction. 8.3.4 referencing execution result of ldsr instruction for eipc and fepc when using the ldsr instruction to set the data of the eipc and fepc system registers, and immediately after referencing the same system registers with the stsr instruction, the use of the system registers for the stsr instruction is delayed until the setting of the system registers with the ldsr instruction is completed (occurrence of hazard). the v850 familys interlock function delays the id stage of the stsr instruction immediately after. as a result of the above, when using the execution result of the ldsr instruction for eipc and fepc for an stsr instruction following immediately after, the number of execution clocks of the ldsr instruction becomes 3. il : idle inserted for data wait by interlock function C : idle inserted for wait note system register 0 used for the ldsr and stsr instructions designates eipc. as described above, when an stsr instruction is placed immediately after an ldsr instruction that uses the operand eipc or fepc, and that stsr instruction uses the ldsr instruction execution result, the interlock function causes a data wait time to occur, and the execution speed is lowered. this drop in execution speed can be avoided by placing stsr instructions that reference the execution result of the preceding ldsr instruction at least 3 instructions after the ldsr instruction. 8.3.5 cautions when creating programs when creating programs, pipeline disorder can be avoided and instruction execution speed can be raised by observing the following cautions. ? place instructions that use the execution result of load instructions (ld, sld) at least 2 instructions after the load instruction. ? place instructions that use the execution result of multiply instructions (mulh, mulhi) at least 2 instructions after the multiply instruction. ? if using the stsr instruction to read the setting results written to the eipc or fepc registers with the ldsr instruction, place the stsr instruction at least 3 instructions after the ldsr instruction. ? for the first branch destination instruction, use a 2-byte instruction, or a 4-byte instruction placed at the word boundary. if id ex mem if il il ex ldsr instruction (ldsr r6, 0) note stsr instruction (stsr 0, r7) note mem if id ex mem if id ex mem wb wb next instruction next to next instruction wb wb id 1234 56 78 9 10
113 chapter 8 pipeline (2) not v850 family (other than harvard architecture) the mem stage of instruction 1 and the if stage of instruction 4, in addition to the mem stage of instruction 2 and the if stage of instruction 5 are in contention, causing path waiting to occur and slower execution time due to disorderly pipeline operation. C : idle inserted for wait 8.4 additional items related to pipeline 8.4.1 harvard architecture the v850 family uses the harvard architecture to operate an instruction fetch path from internal rom and a memory access path to internal ram independently. this eliminates path arbitration conflicts between the if and mem stages and allows orderly pipeline operation. (1) v850 family (harvard architecture) the mem stage of instruction 1 and the if stage of instruction 4, as well as the mem stage of instruction 2 and the if stage of instruction 5 can be executed simultaneously with orderly pipeline operation. if id ex mem if id ex wb instruction 1 instruction 2 if ex mem wb ex mem wb instruction 3 instruction 4 wb mem id instruction 5 id ex mem wb if if id 1234 56 78 9 if id ex mem if id mem instruction 1 instruction 2 if id ex ? id ex instruction 3 instruction 4 wb ex instruction 5 if if id ex 1234 56 78 9 10 wb mem mem mem 11 wb wb wb
chapter 8 pipeline 114 8.4.2 short path the v850 family provides on chip a short path that allows the use of the execution result of the preceding instruction by the following instruction before write back (wb) is completed for the previous instruction. example 1. execution result of arithmetic operation instruction and logical operation used by instruction following immediately after ? v850 family (on-chip short path) the execution result of the preceding instruction can be used for the id stage of the instruction following immediately after as soon as the result is out (ex stage), without having to wait for write back to be completed. ? not v850 family (no short path) the id stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. C : idle inserted for wait : short path example 2. data read from memory by the load instruction used by instruction following immediately after ? v850 family (on-chip short path) the execution result of the preceding instruction can be used for the id stage of the instruction following immediately after as soon as the result is out (mem stage), without having to wait for write back to be completed. ? not v850 family (no short path) the id stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. il : idle inserted for data wait by interlock function C : idle inserted for wait : short path if id ex mem wb if id ex mem wb add 2, r6 mov r6, r7 1234 56 if id ex mem wb ifidex add 2, r6 mov r6, r7 mem wb 1234 56 78 if id ex mem wb if il id ex mem ld [r4], r6 add 2, r6 wb id ex mem id ex mem wb wb next instruction next to next instruction 1234 56 78 9 if if if id ex mem wb ifidex ld [r4], r6 add 2, r6 mem if id ex if id ex mem mem next instruction next to next instruction wb wb wb 1234 56 78 9 10
appendix a instruction mnemonic (in alphabetical order) this appendix summarizes the properties and functions of the v850 familys instructions to allow users to know the outline of the desired instruction quickly. instructions are listed in alphabetical order of their mnemonics. the illustration and table shown below indicates how to read this appendix and what each legend and word means. name meaning reg1 general register (used as source register) reg2 general register (mainly used as destination register. some are also used as source registers) bit#3 3-bit data for bit number specification imm -bit immediate disp -bit displacement regid system register number vector trap handler address corresponding to trap vector cccc 4-bit data for 4-bit condition code specification identifier meaning 0 reset (to 0) * set (to 1) or reset (to 0) according to instruction execution result C no change instruction mnemonic operand name indicates instruction format. describes movements of flags. add reg1, reg2 i * legend instruction mnemonic operand format cy ov s z sat *** 115
appendix a instruction mnemonic (in alphabetical order) 116 table a-1. instruction mnemonic (in alphabetical order) (1/7) instruction operand format cy ov s z sat instruction function mnemonic add reg1, reg2 i * * * * C add. adds the word data of reg1 to the word data of reg2, and stores the result to reg2. add imm5, reg2 ii * * * * C add. adds the 5-bit immediate data, sign- extended to word length, to the word data of reg2, and stores the result to reg2. addi imm16, reg1, reg2 vi * * * * C add. adds the 16-bit immediate data, sign- extended to word length, to the word data of reg1, and stores the result to reg2. and reg1, reg2 i C 0 * * C and. ands the word data of reg2 with the word data of reg1, and stores the result to reg2. andi imm16, reg1, reg2 vi C 0 * * C and. ands the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result to reg2. bcond disp9 iii C C C C C conditional branch (if carry). tests a condition flag specified by an instruction. branches if a specified condition is satisfied; otherwise, executes the next instruction. the branch destination pc holds the sum of the current pc value and 9-bit displacement which is the 8-bit immediate shifted 1 bit and sign-extended to word length. clr1 bit#3, disp16 [reg1] viii C C C * C bit clear. adds the data of reg1 to 16-bit displacement, sign-extended to word length, to generate a 32-bit address. then clears the bit, specified by the instruction bit field, of the byte data referenced by the generated address. cmp reg1, reg2 i * * * * C compare. compares the word data of reg2 with the word data of reg1, and indicates the result by using the condition flags. to compare, the contents of reg1 are subtracted from the word data of reg2. cmp imm5, reg2 ii * * * * C compare. compares the word data of reg2 with the 5-bit immediate data, sign-extended to word length, and indicates the result by using the condition flags. to compare, the contents of the sign-extended immediate data are subtracted from the word data of reg2. di C x C C C C C disables maskable interrupt. sets the id flag of the psw to 1 to disable the acknowledgement of maskable interrupts from acceptance; interrupts are immediately disabled at the start of this instruction execution.
117 appendix a instruction mnemonic (in alphabetical order) table a-1. instruction mnemonic (in alphabetical order) (2/7) instruction operand format cy ov s z sat instruction function mnemonic divh reg1, reg2 i C * * * C signed divide. divides the word data of reg2 by the lower half-word data of reg1, and stores the quotient to reg2. ei C x C C C C C enables maskable interrupt. resets the id flag of the psw to 0 and enables the acknowledge- ment of maskable interrupts at the beginning of next instruction. halt C x C C C C C cpu halt. stops the operating clock of the cpu and places the cpu in the halt mode. jarl disp22, reg2 v C C C C C jump and register link. saves the current pc value plus 4 to general register reg2, adds a 22- bit displacement, sign-extended to word length, to the current pc value, and transfers control to the pc. bit 0 of the 22-bit displacement is masked to 0. jmp [reg1] i C C C C C register indirect unconditional branch. trans- fers control to the address specified by reg1. bit 0 of the address is masked to 0. jr disp22 v C C C C C unconditional branch. adds a 22-bit displace- ment, sign-extended to word length, to the current pc value, and transfers control to the pc. bit 0 of the 22-bit displacement is masked to 0. ld.b disp16 [reg1], reg2 vii C C C C C byte load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. byte data is read from the generated address, sign-extended to word length, and then stored to reg2. ld.h disp16 [reg1], reg2 vii C C C C C half-word load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. half-word data is read from this 32-bit address with its bit 0 masked to 0, sign-extended to word length, and stored to reg2. ld.w disp16 [reg1], reg2 vii C C C C C word load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored to reg2.
appendix a instruction mnemonic (in alphabetical order) 118 table a-1. instruction mnemonic (in alphabetical order) (3/7) instruction operand format cy ov s z sat instruction function mnemonic ldsr reg2, regid ix C C C C C load to system register. set the word data of reg2 to a system register specified by regid. if regid is psw, the values of the corresponding bits of reg2 are set to the respective flags of the psw. mov reg1, reg2 i C C C C C moves data. transfers the word data of reg1 to reg2. mov imm5, reg2 ii C C C C C moves data. transfers the value of a 5-bit immediate data,sign-extended to word length, to reg2. movea imm16, reg1, reg2 vi C C C C C moves effective address. adds a 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result to reg2. movhi imm16, reg1, reg2 vi C C C C C moves higher half-word. adds word data, in which the higher 16 bits are defined by the 16-bit immediate data while the lower 16 bits are set to 0, to the word data of reg1 and stores the result to reg2. mulh reg1, reg2 i C C C C C signed multiply. multiplies the lower half-word data of reg2 by the lower half-word data of reg1, and stores the result to reg2 as word data. mulh imm5, reg2 ii C C C C C signed multiply. multiplies the lower half-word data of reg2 by a 5-bit immediate data, sign- extended to half-word length, and stores the result to reg2 as word data. mulhi imm16, reg1, reg2 vi C C C C C signed multiply. multiplies the lower half-word data of reg1 by a 16-bit immediate data, and stores the result to reg2. nop C i C C C C C no operation. executes nothing and consumes at least one clock cycle. not reg1, reg2 i C 0 * * C logical not. logically negates (takes 1s comple- ment of) the word data of reg1, and stores the result to reg2. not1 bit#3, disp16 [reg1] viii C C C * C bit not. first, adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. the bit specified by the 3-bit field bbb is inverted at the byte data location referenced by the generated address. or reg1, reg2 i C 0 * * C logical sum. ors the word data of reg2 with the word data of reg1, and stores the result to reg2.
119 appendix a instruction mnemonic (in alphabetical order) table a-1. instruction mnemonic (in alphabetical order) (4/7) instruction operand format cy ov s z sat instruction function mnemonic ori imm16, reg1, reg2 vi C 0 * * C logical sum. ors the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result to reg2. reti C x * * * * * returns from exception or interrupt routine. restores the return pc and psw from the appropriate system register, and returns from exception or interrupt routine. sar reg1, reg2 ix * 0 * * C arithmetic right shift. arithmetically shifts the word data of reg2 to the right by n positions, where n is specified by the lower 5 bits of reg1 (the msb prior to shift execution is copied and set as the new msb), and then writes the result to reg2. sar imm5, reg2 ii * 0 * * C arithmetic right shift. arithmetically shifts the word data of reg2 to the right by n positions specified by the 5-bit immediate data, zero-extended to word length (the msb prior to shift execution is copied and set as the new msb), and then writes the result to reg2. satadd reg1, reg2 i * * * * * saturated add. adds the word data of reg1 to the word data of reg2, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satadd imm5, reg2 ii * * * * * saturated add. adds the 5-bit immediate data, sign-extended to word length, to the word data of reg2, and stores the result to general register reg2. however, if the result exceeds the positive maximum value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satsub reg1, reg2 i * * * * * saturated subtract. subtracts the word data of reg1 from the word data of reg2, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1.
appendix a instruction mnemonic (in alphabetical order) 120 table a-1. instruction mnemonic (in alphabetical order) (5/7) instruction operand format cy ov s z sat instruction function mnemonic satsubi imm16, reg1, reg2 vi * * * * * saturated subtract. subtracts a 16-bit immediate sign-extended to word length from the word data of reg1, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. satsubr reg1, reg2 i * * * * * saturated subtract reverse. subtracts the word data of reg2 from the word data of reg1, and stores the result to reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored to reg2; if the result exceeds the maximum negative value, the maximum negative value is stored to reg2. the sat flag is set to 1. setf cccc, reg2 ix C C C C C set flag condition. the reg2 is set to 1 if a condition specified by condition code cccc is satisfied; otherwise, a 0 is stored to the register. set1 bit#3, disp16 [reg1] viii C C C * C bit set. first, adds a 16-bit displacement, sign- extended to word length, to the data of reg1 to generate a 32-bit address. the bits, specified by the 3-bit bit field bbb is set at the byte data location specified by the generated address. shl reg1, reg2 ix * 0 * * C logical left shift. logically shifts the word data of reg2 to the left by n positions (0 is shifted to the lsb side), where n is specified by the lower 5 bits of reg1, and writes the result to reg2. shl imm5, reg2 ii * 0 * * C logical left shift. logically shifts the word data of reg2 to the left by n positions (0 is shifted to the lsb side), where n is specified by a 5-bit immediate data, zero-extended to word length, and writes the result to reg2. shr reg1, reg2 ix * 0 * * C logical right shift. logically shifts the word data of reg2 to the right by n positions (0 is shifted to the msb side), where n is specified by the lower 5 bits of reg1, and writes the result to reg2. shr imm5, reg2 ii * 0 * * C logical right shift. logically shifts the word data of reg2 to the right by n positions (0 is shifted to the msb side), where n is specified by a 5-bit immediate data, zero-extended to word length, and writes the result to reg2.
121 appendix a instruction mnemonic (in alphabetical order) table a-1. instruction mnemonic (in alphabetical order) (6/7) instruction operand format cy ov s z sat instruction function mnemonic sld.b disp7 [ep], reg2 iv C C C C C byte load. adds the 7-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address. byte data is read from the generated address, sign-extended to word length, and stored to reg2. sld.h disp8 [ep], reg2 iv C C C C C half-word load. adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. half-word data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored to reg2. sld.w disp8 [ep], reg2 iv C C C C C word load. adds the 8-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored to reg2. sst.b reg2, disp7 [ep] iv C C C C C byte store. adds the 7-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 to the generated address. sst.h reg2, disp8 [ep] iv C C C C C half-word store. adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower half-word of reg2 to the generated 32- bit address with bit 0 masked to 0. sst.w reg2, disp8 [ep] iv C C C C C word store. adds the 8-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 to the generated 32-bit address with bits 0 and 1 masked to 0. st.b reg2, disp16 [reg1] vii C C C C C byte store. adds the 16-bit displacement, sign- extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lowest byte data of reg2 to the generated address. st.h reg2, disp16 [reg1] vii C C C C C half-word store. adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lower half-word of reg2 to the generated 32-bit address with bit 0 masked to 0.
appendix a instruction mnemonic (in alphabetical order) 122 table a-1. instruction mnemonic (in alphabetical order) (7/7) instruction operand format cy ov s z sat instruction function mnemonic st.w reg2, disp16 [reg1] vii C C C C C word store. adds the 16-bit displacement, sign- extended to word length, to the data of reg1 to generate a 32-bit address, and stores the word data of reg2 to the generated 32-bit address with bits 0 and 1 masked to 0. stsr regid, reg2 ix C C C C C stores contents of system register. stores the contents of a system register specified by regid to reg2. sub reg1, reg2 i * * * * C subtract. subtracts the word data of reg1 from the word data of reg2, and stores the result to reg2. subr reg1, reg2 i * * * * C subtract reverse. subtracts the word data of reg2 from the word data of reg1, and stores the result to reg2. trap vector x C C C C C software trap. saves the return pc and psw to eipc and eipsw, respectively; sets the excep- tion code (eicc of ecr) and the flags of the psw (ep and id flags); jumps to the address of the trap handler corresponding to the trap vector specified by vector number (0 to 31), and starts exception processing. tst reg1, reg2 i C 0 * * C test. ands the word data of reg2 with the word data of reg1. the result is not stored, and only the flags are changed. tst1 bit#3, disp16 [reg1] viii C C C * C bit test. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. performs the test on the bit, specified by the 3-bit field bbb, at the byte data location referenced by the generated address. if the specified bit is 0, the z flag is set to 1; if the bit is 1, the z flag is reset to 0. the byte data, including the specified bit, is not affected. xor reg1, reg2 i C 0 * * C exclusive or. exclusively ors the word data of reg2 with the word data of reg1, and stores the result to reg2. xori imm16, reg1, reg2 vi C 0 * * C exclusive or immediate. exclusively ors the word data of reg1 with a 16-bit immediate data, zero-extended to word length, and stores the result to reg2.
appendix b instruction list table b-1. mnemonic list mnemonic function load/store ld.b load byte ld.h load halfword ld.w lord word sld.b load byte sld.h load halfword sld.w load word st.b store byte st.h store halfword st.w store word sst.b store byte sst.h store halfword sst.w store word integer arithmetic operation/logical operation/saturated operation (2-operand register) mov move add add sub subtract subr subtract reverse mulh multiply halfword divh divide halfword cmp compare satadd saturated add satsub saturated subtract satsubr saturated subtract reverse tst test or or and and xor exclusive or not not shl shift logical left shr shift logical right sar shift arithmetic right (2-operand immediate) mov move add add cmp compare satadd saturated add setf set flag condition shl shift logical left shr shift logical right sar shift arithmetic right (3-operand) movhi move high halfword movea move effective address addi add immediate mulhi multiply halfword immediate satsubi saturated subtract immediate ori or lmmediate andi and immediate xori exclusive or immediate branch jmp jump register jr jump relative jarl jump and register link bcond branch on condition code bit manipulation set1 set bit clr1 clear bit not1 not bit tst1 test bit special ldsr load system register stsr store system register trap trap reti return from trap or interrupt halt halt di disable interrupt ei enable interrupt nop no operation mnemonic function 123
appendix b instruction list 124 table b-2. instruction set instruction code instruction format format remarks 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 mov reg1, reg2 not reg1, reg2 divh reg1, reg2 jmp [reg1] satsubr reg1, reg2 satsub reg1, reg2 satadd reg1, reg2 mulh reg1, reg2 or reg1, reg2 xor reg1, reg2 and reg1, reg2 tst reg1, reg2 subr reg1, reg2 sub reg1, reg2 add reg1, reg2 cmp reg1, reg2 mov imm5, reg2 satadd imm5, reg2 add imm5, reg2 cmp imm5, reg2 shr imm5, reg2 sar imm5, reg2 shl imm5, reg2 mulh imm5, reg2 sld.b disp7 [ep], reg2 sst.b reg2, disp7 [ep] sld.h disp8 [ep], reg2 sst.h reg2, disp8 [ep] sld.w disp8 [ep], reg2 sst.w reg2, disp8 [ep] bcond disp9 addi imm16, reg1, reg2 movea imm16, reg1, reg2 movhi imm16, reg1, reg2 satsubi imm16, reg1, reg2 ori imm16, reg1, reg2 xori imm16, reg1, reg2 andi imm16, reg1, reg2 mulhi imm16, reg1, reg2 ld.b disp16 [reg1], reg2 ld.h disp16 [reg1], reg2 ld.w disp16 [reg1], reg2 st.b reg2, disp16 [reg1] st.h reg2, disp16 [reg1] st.w reg2, disp16 [reg1] jarl disp22, reg2 set1 bit#3, disp16 [reg1] clr1 bit#3, disp16 [reg1] not1 bit#3, disp16 [reg1] tst1 bit#3, disp16 [reg1] setf cccc, reg2 ldsr reg2, regid stsr regid, reg2 shr reg1, reg2 sar reg1, reg2 shl reg1, reg2 trap vector halt reti di ei undefined instruction i ii iv iii vi vii v viii ix x when reg2 = r0, jr disp22 when reg1, reg2 = 0, nop
appendix c instruction op code map the following tables (a) through (f) show the op code maps corresponding to instruction codes. instruction code ? 16-bit instruction format ? 32-bit instruction format (a) op code bits 6 - 5 00 01 10 11 format bits 10 - 7 0000 mov/nop not divh jmp i 0001 satsubr satsub satadd mulh 0010 or xor and tst 0011 subr sub add r, r cmp r,r 0100 mov imm5, r satadd add imm5, r cmp imm5, r ii 0101 shr imm5, r sar imm5, r shl imm5, r mulh 0110 sld.b iv 0111 sst.b 1000 sld.h 1001 sst.h 1010 sld. w/sst.w note 1 1011 bcond iii 1100 addi movea movhi satsubi vi 1101 ori xori andi mulhi 1110 ld.b ld.h/ld.w note 2 st.b st.h/st.w note 2 v/vii/viii/ix/x 1111 jarl bit manipulation note 3 extension 1 note 4 notes 1. refer to (b) . 2. refer to (c) . 3. refer to (d) . 4. refer to (e) . 15 11 10 5 4 0 op code (refer to (a) ) sub op code (refer to (b) ) 15 11 10 5 4 0 14 13 12 31 27 26 21 20 17 16 op code (refer to (a) ) sub-op code (refer to (d) ) sub-op code (refer to (f) ) sub-op code (refer to (e) ) sub-op code (refer to (c) ) 125
appendix c instruction op code map 126 (b) short format load/store instruction (displacement/sub-op code) bit 0 01 bits 10 - 7 0110 sld.b 0111 sst.b 1000 sld.h 1001 sst.h 1010 sld.w sst.w (c) load/store instruction (displacement/sub-op code) bit 16 01 bits 6 - 5 00 ld.b 01 ld.h ld.w 10 st.b 11 st.h st.w (d) bit manipulation instruction (sub-op code) bit 14 01 bit 15 0 set1 not1 1 clr1 tst1 (e) extension 1 (sub-op code) bits 22 - 21 00 01 10 11 bits 26 - 23 0000 setf ldsr stsr undefined 0001 shr r, r sar r, r shl r, r undefined 0010 trap halt reti extension 2 note 0011 illegal instruction 1111 note refer to (f) . (f) extension 2 (sub-op code) bits 14 - 13 00 01 10 11 bit 15 0 di undefined 1ei ~
addressing modes operand address ........................... 22 based addressing ....................... 22 bit addressing .............................. 24 immediate addressing ................ 22 register addressing .................... 22 instruction address ......................... 19 register addressing .................... 21 relative addressing .................... 19 data format alignment ........................................ 15 representation ............................... 14 types ............................................... 13 execution clock ................................... 92 instruction format 3-operand ........................................ 26 16-bit load/store .............................. 26 32-bit load/store .............................. 26 bit manipulation .............................. 27 conditional branch ......................... 25 extended format ............................. 27 imm-reg ........................................... 25 jump ................................................ 26 reg-reg ............................................. 25 memory map ....................................... 18 program registers ................................ 6 program status word ........................... 9 system registers .................................. 8 system register number ............... 11 _____________________________ index add ..................................................... 36 addi .................................................... 37 and ..................................................... 38 andi .................................................... 39 bcond .................................................. 40 clr1 .................................................... 42 cmp ..................................................... 43 di ...................................................... 44 divh .................................................... 45 ei ...................................................... 46 halt .................................................... 47 jarl .................................................... 48 jmp ...................................................... 49 jr ...................................................... 50 ld ...................................................... 51 ldsr ................................................... 53 mov ..................................................... 54 movea ................................................ 55 movhi ................................................. 56 mulh ................................................... 57 mulhi ................................................. 58 nop ..................................................... 59 not ..................................................... 60 not1 ................................................... 61 or ...................................................... 62 ori ...................................................... 63 reti ..................................................... 64 sar ..................................................... 66 satadd .............................................. 67 satsub .............................................. 68 127
index 128 satsubi ............................................. 69 satsubr ........................................... 70 setf .................................................... 71 set1 .................................................... 73 shl ...................................................... 74 shr ..................................................... 75 sld ...................................................... 76 sst ...................................................... 78 st ...................................................... 80 stsr ................................................... 82 sub ..................................................... 83 subr ................................................... 84 trap ................................................... 85 tst ...................................................... 86 tst1 .................................................... 87 xor ..................................................... 88 xori .................................................... 89 _____________________________
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